1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 14import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 15 16class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 17{ 18 val csrIn = io.csrio.get 19 val csrOut = io.csrio.get 20 val csrToDecode = io.csrToDecode.get 21 22 val setFsDirty = csrIn.fpu.dirty_fs 23 val setFflags = csrIn.fpu.fflags 24 val setVsDirty = csrIn.vpu.dirty_vs 25 val setVxsat = csrIn.vpu.vxsat 26 val setVstart = csrIn.vpu.set_vstart 27 val setVl = csrIn.vpu.set_vl 28 val setVtype = 0.U.asTypeOf(csrIn.vpu.set_vtype) 29 30 val flushPipe = Wire(Bool()) 31 val flush = io.flush.valid 32 33 val (valid, src1, src2, func) = ( 34 io.in.valid, 35 io.in.bits.data.src(0), 36 io.in.bits.data.imm, 37 io.in.bits.ctrl.fuOpType 38 ) 39 40 // split imm from IMM_Z 41 val addr = src2(11, 0) 42 val csri = ZeroExt(src2(16, 12), XLEN) 43 44 import CSRConst._ 45 46 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 47 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 48 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 49 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 50 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 51 private val isWfi = CSROpType.isWfi(func) 52 private val isCSRAcc = CSROpType.isCsrAccess(func) 53 54 val csrMod = Module(new NewCSR) 55 56 private val privState = csrMod.io.out.privState 57 // The real reg value in CSR, with no read mask 58 private val regOut = csrMod.io.out.regOut 59 // The read data with read mask 60 private val rdata = csrMod.io.out.rData 61 private val wdata = LookupTree(func, Seq( 62 CSROpType.wrt -> src1, 63 CSROpType.set -> (regOut | src1), 64 CSROpType.clr -> (regOut & (~src1).asUInt), 65 CSROpType.wrti -> csri, 66 CSROpType.seti -> (regOut | csri), 67 CSROpType.clri -> (regOut & (~csri).asUInt), 68 )) 69 70 private val csrAccess = valid && CSROpType.isCsrAccess(func) 71 private val csrWen = valid && CSROpType.notReadOnly(func) 72 73 csrMod.io.in match { 74 case in => 75 in.wen := csrWen 76 in.ren := csrAccess 77 in.addr := addr 78 in.wdata := wdata 79 } 80 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 81 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 82 83 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 84 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 85 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 86 // Todo: shrink the width of trap vector. 87 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 88 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 89 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 90 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 91 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 92 csrMod.io.fromRob.trap.bits.triggerCf := csrIn.exception.bits.trigger 93 94 csrMod.io.fromRob.commit.fflags := setFflags 95 csrMod.io.fromRob.commit.fsDirty := setFsDirty 96 csrMod.io.fromRob.commit.vxsat.valid := setVxsat 97 csrMod.io.fromRob.commit.vxsat.bits := setVxsat 98 csrMod.io.fromRob.commit.vsDirty := setVsDirty 99 csrMod.io.fromRob.commit.vstart := setVstart 100 csrMod.io.fromRob.commit.vl := setVl 101 // Todo: correct vtype 102 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 103 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 104 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 105 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 106 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 107 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 108 109 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 110 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 111 112 csrMod.io.mret := isMret && valid 113 csrMod.io.sret := isSret && valid 114 csrMod.io.dret := isDret && valid 115 csrMod.io.wfi := isWfi && valid 116 csrMod.io.ebreak := isEbreak && valid 117 118 csrMod.io.perf := csrIn.perf 119 120 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 121 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 122 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 123 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 124 csrMod.platformIRP.STIP := false.B 125 csrMod.platformIRP.VSEIP := false.B // Todo 126 csrMod.platformIRP.VSTIP := false.B // Todo 127 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 128 129 csrMod.io.fromTop.hartId := io.csrin.get.hartId 130 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 131 132 private val imsic = Module(new IMSIC) 133 imsic.i.hartId := io.csrin.get.hartId 134 imsic.i.msiInfo := io.csrin.get.msiInfo 135 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 136 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 137 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 138 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 139 imsic.i.csr.vgein := csrMod.toAIA.vgein 140 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 141 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 142 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 143 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 144 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 145 146 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 147 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 148 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 149 csrMod.fromAIA.mtopei.valid := imsic.o.mtopei.valid 150 csrMod.fromAIA.stopei.valid := imsic.o.stopei.valid 151 csrMod.fromAIA.vstopei.valid := imsic.o.vstopei.valid 152 csrMod.fromAIA.mtopei.bits := imsic.o.mtopei.bits 153 csrMod.fromAIA.stopei.bits := imsic.o.stopei.bits 154 csrMod.fromAIA.vstopei.bits := imsic.o.vstopei.bits 155 156 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 157 import ExceptionNO._ 158 exceptionVec(EX_BP ) := isEbreak 159 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 160 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 161 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 162 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 163 exceptionVec(EX_II ) := csrMod.io.out.EX_II 164 exceptionVec(EX_VI ) := csrMod.io.out.EX_VI 165 166 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 167 168 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 169 val isXRetFlag = RegInit(false.B) 170 isXRetFlag := Mux1H(Seq( 171 DelayN(flush, 5) -> false.B, 172 isXRet -> true.B, 173 )) 174 175 flushPipe := csrMod.io.out.flushPipe 176 177 // tlb 178 val tlb = Wire(new TlbCsrBundle) 179 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 180 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 181 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 182 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 183 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 184 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 185 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 186 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 187 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 188 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 189 tlb.hgatp.asid := csrMod.io.tlb.hgatp.VMID.asUInt 190 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 191 192 // expose several csr bits for tlb 193 tlb.priv.mxr := csrMod.io.tlb.mxr 194 tlb.priv.sum := csrMod.io.tlb.sum 195 tlb.priv.vmxr := csrMod.io.tlb.vmxr 196 tlb.priv.vsum := csrMod.io.tlb.vsum 197 tlb.priv.spvp := csrMod.io.tlb.spvp 198 tlb.priv.virt := csrMod.io.out.privState.V.asBool 199 tlb.priv.imode := csrMod.io.tlb.imode 200 tlb.priv.dmode := csrMod.io.tlb.dmode 201 202 io.in.ready := true.B // Todo: Async read imsic may block CSR 203 io.out.valid := valid 204 io.out.bits.ctrl.exceptionVec.get := exceptionVec 205 io.out.bits.ctrl.flushPipe.get := flushPipe 206 io.out.bits.res.data := csrMod.io.out.rData 207 208 io.out.bits.res.redirect.get.valid := isXRet 209 val redirect = io.out.bits.res.redirect.get.bits 210 redirect := 0.U.asTypeOf(redirect) 211 redirect.level := RedirectLevel.flushAfter 212 redirect.robIdx := io.in.bits.ctrl.robIdx 213 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 214 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 215 redirect.cfiUpdate.predTaken := true.B 216 redirect.cfiUpdate.taken := true.B 217 redirect.cfiUpdate.target := csrMod.io.out.targetPc 218 // Only mispred will send redirect to frontend 219 redirect.cfiUpdate.isMisPred := true.B 220 221 connect0LatencyCtrlSingal 222 223 // Todo: summerize all difftest skip condition 224 csrOut.isPerfCnt := csrMod.io.out.isPerfCnt && valid && func =/= CSROpType.jmp 225 csrOut.fpu.frm := csrMod.io.out.fpState.frm.asUInt 226 csrOut.vpu.vstart := csrMod.io.out.vecState.vstart.asUInt 227 csrOut.vpu.vxsat := csrMod.io.out.vecState.vxsat.asUInt 228 csrOut.vpu.vxrm := csrMod.io.out.vecState.vxrm.asUInt 229 csrOut.vpu.vcsr := csrMod.io.out.vecState.vcsr.asUInt 230 csrOut.vpu.vl := csrMod.io.out.vecState.vl.asUInt 231 csrOut.vpu.vtype := csrMod.io.out.vecState.vtype.asUInt 232 csrOut.vpu.vlenb := csrMod.io.out.vecState.vlenb.asUInt 233 csrOut.vpu.vill := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VILL.asUInt 234 csrOut.vpu.vma := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VMA.asUInt 235 csrOut.vpu.vta := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VTA.asUInt 236 csrOut.vpu.vsew := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VSEW.asUInt 237 csrOut.vpu.vlmul := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VLMUL.asUInt 238 239 csrOut.isXRet := isXRetFlag 240 241 csrOut.trapTarget := csrMod.io.out.targetPc 242 csrOut.interrupt := csrMod.io.out.interrupt 243 csrOut.wfi_event := csrMod.io.out.wfiEvent 244 245 csrOut.tlb := tlb 246 247 csrOut.debugMode := csrMod.io.out.debugMode 248 249 // Todo: this bundle should be used in decode. 250 // Todo: check permission in decode stage, pass tvm and vtvm only 251 csrOut.disableSfence := Mux( 252 csrMod.io.out.tvm, 253 csrMod.io.out.privState < PrivState.ModeM, 254 csrMod.io.out.privState.PRVM < PrivMode.S 255 ) 256 csrOut.disableHfencev := DontCare // Todo 257 csrOut.disableHfenceg := DontCare // Todo 258 259 csrOut.customCtrl match { 260 case custom => 261 custom.l1I_pf_enable := csrMod.io.out.custom.l1I_pf_enable 262 custom.l2_pf_enable := csrMod.io.out.custom.l2_pf_enable 263 custom.l1D_pf_enable := csrMod.io.out.custom.l1D_pf_enable 264 custom.l1D_pf_train_on_hit := csrMod.io.out.custom.l1D_pf_train_on_hit 265 custom.l1D_pf_enable_agt := csrMod.io.out.custom.l1D_pf_enable_agt 266 custom.l1D_pf_enable_pht := csrMod.io.out.custom.l1D_pf_enable_pht 267 custom.l1D_pf_active_threshold := csrMod.io.out.custom.l1D_pf_active_threshold 268 custom.l1D_pf_active_stride := csrMod.io.out.custom.l1D_pf_active_stride 269 custom.l1D_pf_enable_stride := csrMod.io.out.custom.l1D_pf_enable_stride 270 custom.l2_pf_store_only := csrMod.io.out.custom.l2_pf_store_only 271 // ICache 272 custom.icache_parity_enable := csrMod.io.out.custom.icache_parity_enable 273 // Load violation predictor 274 custom.lvpred_disable := csrMod.io.out.custom.lvpred_disable 275 custom.no_spec_load := csrMod.io.out.custom.no_spec_load 276 custom.storeset_wait_store := csrMod.io.out.custom.storeset_wait_store 277 custom.storeset_no_fast_wakeup := csrMod.io.out.custom.storeset_no_fast_wakeup 278 custom.lvpred_timeout := csrMod.io.out.custom.lvpred_timeout 279 // Branch predictor 280 custom.bp_ctrl := csrMod.io.out.custom.bp_ctrl 281 // Memory Block 282 custom.sbuffer_threshold := csrMod.io.out.custom.sbuffer_threshold 283 custom.ldld_vio_check_enable := csrMod.io.out.custom.ldld_vio_check_enable 284 custom.soft_prefetch_enable := csrMod.io.out.custom.soft_prefetch_enable 285 custom.cache_error_enable := csrMod.io.out.custom.cache_error_enable 286 custom.uncache_write_outstanding_enable := csrMod.io.out.custom.uncache_write_outstanding_enable 287 // Rename 288 custom.fusion_enable := csrMod.io.out.custom.fusion_enable 289 custom.wfi_enable := csrMod.io.out.custom.wfi_enable 290 // distribute csr write signal 291 // write to frontend and memory 292 custom.distribute_csr.w.valid := csrWen 293 custom.distribute_csr.w.bits.addr := addr 294 custom.distribute_csr.w.bits.data := wdata 295 // rename single step 296 custom.singlestep := csrMod.io.out.singleStepFlag 297 // trigger 298 custom.frontend_trigger.tUpdate.valid := csrMod.io.out.frontendTrigger.tUpdate.valid 299 custom.frontend_trigger.tUpdate.bits.addr := csrMod.io.out.frontendTrigger.tUpdate.bits.addr 300 custom.frontend_trigger.tUpdate.bits.tdata := csrMod.io.out.frontendTrigger.tUpdate.bits.tdata 301 custom.frontend_trigger.tEnableVec := csrMod.io.out.frontendTrigger.tEnableVec 302 custom.mem_trigger.tUpdate.valid := csrMod.io.out.memTrigger.tUpdate.valid 303 custom.mem_trigger.tUpdate.bits.addr := csrMod.io.out.memTrigger.tUpdate.bits.addr 304 custom.mem_trigger.tUpdate.bits.tdata := csrMod.io.out.memTrigger.tUpdate.bits.tdata 305 custom.mem_trigger.tEnableVec := csrMod.io.out.memTrigger.tEnableVec 306 // virtual mode 307 custom.virtMode := csrMod.io.out.privState.V.asBool 308 } 309 310 csrToDecode := csrMod.io.toDecode 311} 312 313class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 314 val hartId = Input(UInt(8.W)) 315 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 316 val clintTime = Input(ValidIO(UInt(64.W))) 317} 318 319class CSRToDecode(implicit p: Parameters) extends XSBundle { 320 val illegalInst = new Bundle { 321 /** 322 * illegal sfence.vma, sinval.vma 323 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 324 */ 325 val sfenceVMA = Bool() 326 327 /** 328 * illegal sfence.w.inval sfence.inval.ir 329 * raise EX_II when isModeHU 330 */ 331 val sfencePart = Bool() 332 333 /** 334 * illegal hfence.gvma, hinval.gvma 335 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 336 * the condition is the same as sfenceVMA 337 */ 338 val hfenceGVMA = Bool() 339 340 /** 341 * illegal hfence.vvma, hinval.vvma 342 * raise EX_II when isModeHU 343 */ 344 val hfenceVVMA = Bool() 345 346 /** 347 * illegal hlv, hlvx, and hsv 348 * raise EX_II when isModeHU && hstatus.HU=0 349 */ 350 val hlsv = Bool() 351 352 /** 353 * decode all fp inst 354 * raise EX_II when FS=Off 355 */ 356 val fsIsOff = Bool() 357 358 /** 359 * decode all vec inst 360 * raise EX_II when VS=Off 361 */ 362 val vsIsOff = Bool() 363 364 /** 365 * illegal wfi 366 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 367 */ 368 val wfi = Bool() 369 } 370 val virtualInst = new Bundle { 371 /** 372 * illegal sfence.vma, svinval.vma 373 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 374 */ 375 val sfenceVMA = Bool() 376 377 /** 378 * illegal sfence.w.inval sfence.inval.ir 379 * raise EX_VI when isModeVU 380 */ 381 val sfencePart = Bool() 382 383 /** 384 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 385 * raise EX_VI when isModeVS || isModeVU 386 */ 387 val hfence = Bool() 388 389 /** 390 * illegal hlv, hlvx, and hsv 391 * raise EX_VI when isModeVS || isModeVU 392 */ 393 val hlsv = Bool() 394 395 /** 396 * illegal wfi 397 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 398 */ 399 val wfi = Bool() 400 } 401}