1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 14import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 15 16class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 17{ 18 val csrIn = io.csrio.get 19 val csrOut = io.csrio.get 20 val csrToDecode = io.csrToDecode.get 21 22 val setFsDirty = csrIn.fpu.dirty_fs 23 val setFflags = csrIn.fpu.fflags 24 val setVsDirty = csrIn.vpu.dirty_vs 25 val setVxsat = csrIn.vpu.vxsat 26 val setVstart = csrIn.vpu.set_vstart 27 val setVl = csrIn.vpu.set_vl 28 val setVtype = 0.U.asTypeOf(csrIn.vpu.set_vtype) 29 30 val flushPipe = Wire(Bool()) 31 val flush = io.flush.valid 32 33 val (valid, src1, src2, func) = ( 34 io.in.valid, 35 io.in.bits.data.src(0), 36 io.in.bits.data.imm, 37 io.in.bits.ctrl.fuOpType 38 ) 39 40 // split imm from IMM_Z 41 val addr = src2(11, 0) 42 val csri = ZeroExt(src2(16, 12), XLEN) 43 44 import CSRConst._ 45 46 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 47 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 48 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 49 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 50 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 51 private val isWfi = CSROpType.isWfi(func) 52 private val isCSRAcc = CSROpType.isCsrAccess(func) 53 54 val csrMod = Module(new NewCSR) 55 56 private val privState = csrMod.io.out.privState 57 // The real reg value in CSR, with no read mask 58 private val regOut = csrMod.io.out.regOut 59 // The read data with read mask 60 private val rdata = csrMod.io.out.rData 61 private val wdata = LookupTree(func, Seq( 62 CSROpType.wrt -> src1, 63 CSROpType.set -> (regOut | src1), 64 CSROpType.clr -> (regOut & (~src1).asUInt), 65 CSROpType.wrti -> csri, 66 CSROpType.seti -> (regOut | csri), 67 CSROpType.clri -> (regOut & (~csri).asUInt), 68 )) 69 70 private val csrAccess = valid && CSROpType.isCsrAccess(func) 71 private val csrWen = valid && CSROpType.notReadOnly(func) 72 73 csrMod.io.in match { 74 case in => 75 in.wen := csrWen 76 in.ren := csrAccess 77 in.addr := addr 78 in.wdata := wdata 79 } 80 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 81 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 82 83 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 84 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 85 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 86 // Todo: shrink the width of trap vector. 87 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 88 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 89 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 90 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 91 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 92 csrMod.io.fromRob.trap.bits.triggerCf := csrIn.exception.bits.trigger 93 94 csrMod.io.fromRob.commit.fflags := setFflags 95 csrMod.io.fromRob.commit.fsDirty := setFsDirty 96 csrMod.io.fromRob.commit.vxsat.valid := setVxsat 97 csrMod.io.fromRob.commit.vxsat.bits := setVxsat 98 csrMod.io.fromRob.commit.vsDirty := setVsDirty 99 csrMod.io.fromRob.commit.vstart := setVstart 100 csrMod.io.fromRob.commit.vl := setVl 101 // Todo: correct vtype 102 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 103 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 104 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 105 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 106 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 107 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 108 109 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 110 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 111 112 csrMod.io.mret := isMret && valid 113 csrMod.io.sret := isSret && valid 114 csrMod.io.dret := isDret && valid 115 csrMod.io.wfi := isWfi && valid 116 csrMod.io.ebreak := isEbreak && valid 117 118 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 119 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 120 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 121 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 122 csrMod.platformIRP.VSEIP := false.B // Todo 123 csrMod.platformIRP.VSTIP := false.B // Todo 124 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 125 126 csrMod.io.fromTop.hartId := io.csrin.get.hartId 127 128 private val imsic = Module(new IMSIC) 129 imsic.i.hartId := io.csrin.get.hartId 130 imsic.i.msiInfo := io.csrin.get.msiInfo 131 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 132 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 133 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 134 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 135 imsic.i.csr.vgein := csrMod.toAIA.vgein 136 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 137 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 138 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 139 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 140 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 141 142 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 143 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 144 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 145 csrMod.fromAIA.mtopei.valid := imsic.o.mtopei.valid 146 csrMod.fromAIA.stopei.valid := imsic.o.stopei.valid 147 csrMod.fromAIA.vstopei.valid := imsic.o.vstopei.valid 148 csrMod.fromAIA.mtopei.bits := imsic.o.mtopei.bits 149 csrMod.fromAIA.stopei.bits := imsic.o.stopei.bits 150 csrMod.fromAIA.vstopei.bits := imsic.o.vstopei.bits 151 152 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 153 import ExceptionNO._ 154 exceptionVec(EX_BP ) := isEbreak 155 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 156 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 157 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 158 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 159 exceptionVec(EX_II ) := csrMod.io.out.EX_II 160 exceptionVec(EX_VI ) := csrMod.io.out.EX_VI 161 162 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 163 164 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 165 val isXRetFlag = RegInit(false.B) 166 isXRetFlag := Mux1H(Seq( 167 DelayN(flush, 5) -> false.B, 168 isXRet -> true.B, 169 )) 170 171 flushPipe := csrMod.io.out.flushPipe 172 173 // tlb 174 val tlb = Wire(new TlbCsrBundle) 175 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 176 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 177 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 178 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 179 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 180 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 181 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 182 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 183 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 184 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 185 tlb.hgatp.asid := csrMod.io.tlb.hgatp.VMID.asUInt 186 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 187 188 // expose several csr bits for tlb 189 tlb.priv.mxr := csrMod.io.tlb.mxr 190 tlb.priv.sum := csrMod.io.tlb.sum 191 tlb.priv.vmxr := csrMod.io.tlb.vmxr 192 tlb.priv.vsum := csrMod.io.tlb.vsum 193 tlb.priv.spvp := csrMod.io.tlb.spvp 194 tlb.priv.virt := csrMod.io.out.privState.V.asBool 195 tlb.priv.imode := csrMod.io.tlb.imode 196 tlb.priv.dmode := csrMod.io.tlb.dmode 197 198 io.in.ready := true.B // Todo: Async read imsic may block CSR 199 io.out.valid := valid 200 io.out.bits.ctrl.exceptionVec.get := exceptionVec 201 io.out.bits.ctrl.flushPipe.get := flushPipe 202 io.out.bits.res.data := csrMod.io.out.rData 203 204 io.out.bits.res.redirect.get.valid := isXRet 205 val redirect = io.out.bits.res.redirect.get.bits 206 redirect := 0.U.asTypeOf(redirect) 207 redirect.level := RedirectLevel.flushAfter 208 redirect.robIdx := io.in.bits.ctrl.robIdx 209 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 210 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 211 redirect.cfiUpdate.predTaken := true.B 212 redirect.cfiUpdate.taken := true.B 213 redirect.cfiUpdate.target := csrMod.io.out.targetPc 214 // Only mispred will send redirect to frontend 215 redirect.cfiUpdate.isMisPred := true.B 216 217 connect0LatencyCtrlSingal 218 219 // Todo: summerize all difftest skip condition 220 csrOut.isPerfCnt := csrMod.io.out.isPerfCnt && valid && func =/= CSROpType.jmp 221 csrOut.fpu.frm := csrMod.io.out.fpState.frm.asUInt 222 csrOut.vpu.vstart := csrMod.io.out.vecState.vstart.asUInt 223 csrOut.vpu.vxsat := csrMod.io.out.vecState.vxsat.asUInt 224 csrOut.vpu.vxrm := csrMod.io.out.vecState.vxrm.asUInt 225 csrOut.vpu.vcsr := csrMod.io.out.vecState.vcsr.asUInt 226 csrOut.vpu.vl := csrMod.io.out.vecState.vl.asUInt 227 csrOut.vpu.vtype := csrMod.io.out.vecState.vtype.asUInt 228 csrOut.vpu.vlenb := csrMod.io.out.vecState.vlenb.asUInt 229 csrOut.vpu.vill := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VILL.asUInt 230 csrOut.vpu.vma := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VMA.asUInt 231 csrOut.vpu.vta := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VTA.asUInt 232 csrOut.vpu.vsew := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VSEW.asUInt 233 csrOut.vpu.vlmul := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VLMUL.asUInt 234 235 csrOut.isXRet := isXRetFlag 236 237 csrOut.trapTarget := csrMod.io.out.targetPc 238 csrOut.interrupt := csrMod.io.out.interrupt 239 csrOut.wfi_event := csrMod.io.out.wfiEvent 240 241 csrOut.tlb := tlb 242 243 csrOut.debugMode := csrMod.io.out.debugMode 244 245 // Todo: this bundle should be used in decode. 246 // Todo: check permission in decode stage, pass tvm and vtvm only 247 csrOut.disableSfence := Mux( 248 csrMod.io.out.tvm, 249 csrMod.io.out.privState < PrivState.ModeM, 250 csrMod.io.out.privState.PRVM < PrivMode.S 251 ) 252 csrOut.disableHfencev := DontCare // Todo 253 csrOut.disableHfenceg := DontCare // Todo 254 255 csrOut.customCtrl match { 256 case custom => 257 custom.l1I_pf_enable := csrMod.io.out.custom.l1I_pf_enable 258 custom.l2_pf_enable := csrMod.io.out.custom.l2_pf_enable 259 custom.l1D_pf_enable := csrMod.io.out.custom.l1D_pf_enable 260 custom.l1D_pf_train_on_hit := csrMod.io.out.custom.l1D_pf_train_on_hit 261 custom.l1D_pf_enable_agt := csrMod.io.out.custom.l1D_pf_enable_agt 262 custom.l1D_pf_enable_pht := csrMod.io.out.custom.l1D_pf_enable_pht 263 custom.l1D_pf_active_threshold := csrMod.io.out.custom.l1D_pf_active_threshold 264 custom.l1D_pf_active_stride := csrMod.io.out.custom.l1D_pf_active_stride 265 custom.l1D_pf_enable_stride := csrMod.io.out.custom.l1D_pf_enable_stride 266 custom.l2_pf_store_only := csrMod.io.out.custom.l2_pf_store_only 267 // ICache 268 custom.icache_parity_enable := csrMod.io.out.custom.icache_parity_enable 269 // Load violation predictor 270 custom.lvpred_disable := csrMod.io.out.custom.lvpred_disable 271 custom.no_spec_load := csrMod.io.out.custom.no_spec_load 272 custom.storeset_wait_store := csrMod.io.out.custom.storeset_wait_store 273 custom.storeset_no_fast_wakeup := csrMod.io.out.custom.storeset_no_fast_wakeup 274 custom.lvpred_timeout := csrMod.io.out.custom.lvpred_timeout 275 // Branch predictor 276 custom.bp_ctrl := csrMod.io.out.custom.bp_ctrl 277 // Memory Block 278 custom.sbuffer_threshold := csrMod.io.out.custom.sbuffer_threshold 279 custom.ldld_vio_check_enable := csrMod.io.out.custom.ldld_vio_check_enable 280 custom.soft_prefetch_enable := csrMod.io.out.custom.soft_prefetch_enable 281 custom.cache_error_enable := csrMod.io.out.custom.cache_error_enable 282 custom.uncache_write_outstanding_enable := csrMod.io.out.custom.uncache_write_outstanding_enable 283 // Rename 284 custom.fusion_enable := csrMod.io.out.custom.fusion_enable 285 custom.wfi_enable := csrMod.io.out.custom.wfi_enable 286 // distribute csr write signal 287 // write to frontend and memory 288 custom.distribute_csr.w.valid := csrWen 289 custom.distribute_csr.w.bits.addr := addr 290 custom.distribute_csr.w.bits.data := wdata 291 // rename single step 292 custom.singlestep := csrMod.io.out.singleStepFlag 293 // trigger 294 custom.frontend_trigger.tUpdate.valid := csrMod.io.out.frontendTrigger.tUpdate.valid 295 custom.frontend_trigger.tUpdate.bits.addr := csrMod.io.out.frontendTrigger.tUpdate.bits.addr 296 custom.frontend_trigger.tUpdate.bits.tdata := csrMod.io.out.frontendTrigger.tUpdate.bits.tdata 297 custom.frontend_trigger.tEnableVec := csrMod.io.out.frontendTrigger.tEnableVec 298 custom.mem_trigger.tUpdate.valid := csrMod.io.out.memTrigger.tUpdate.valid 299 custom.mem_trigger.tUpdate.bits.addr := csrMod.io.out.memTrigger.tUpdate.bits.addr 300 custom.mem_trigger.tUpdate.bits.tdata := csrMod.io.out.memTrigger.tUpdate.bits.tdata 301 custom.mem_trigger.tEnableVec := csrMod.io.out.memTrigger.tEnableVec 302 // virtual mode 303 custom.virtMode := csrMod.io.out.privState.V.asBool 304 } 305 306 csrToDecode := csrMod.io.toDecode 307} 308 309class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 310 val hartId = Input(UInt(8.W)) 311 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 312} 313 314class CSRToDecode(implicit p: Parameters) extends XSBundle { 315 val illegalInst = new Bundle { 316 /** 317 * illegal sfence.vma, sinval.vma 318 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 319 */ 320 val sfenceVMA = Bool() 321 322 /** 323 * illegal sfence.w.inval sfence.inval.ir 324 * raise EX_II when isModeHU 325 */ 326 val sfencePart = Bool() 327 328 /** 329 * illegal hfence.gvma, hinval.gvma 330 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 331 * the condition is the same as sfenceVMA 332 */ 333 val hfenceGVMA = Bool() 334 335 /** 336 * illegal hfence.vvma, hinval.vvma 337 * raise EX_II when isModeHU 338 */ 339 val hfenceVVMA = Bool() 340 341 /** 342 * illegal hlv, hlvx, and hsv 343 * raise EX_II when isModeHU && hstatus.HU=0 344 */ 345 val hlsv = Bool() 346 347 /** 348 * decode all fp inst 349 * raise EX_II when FS=Off 350 */ 351 val fsIsOff = Bool() 352 353 /** 354 * decode all vec inst 355 * raise EX_II when VS=Off 356 */ 357 val vsIsOff = Bool() 358 } 359 val virtualInst = new Bundle { 360 /** 361 * illegal sfence.vma, svinval.vma 362 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 363 */ 364 val sfenceVMA = Bool() 365 366 /** 367 * illegal sfence.w.inval sfence.inval.ir 368 * raise EX_VI when isModeVU 369 */ 370 val sfencePart = Bool() 371 372 /** 373 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 374 * raise EX_VI when isModeVS || isModeVU 375 */ 376 val hfence = Bool() 377 378 /** 379 * illegal hlv, hlvx, and hsv 380 * raise EX_VI when isModeVS || isModeVU 381 */ 382 val hlsv = Bool() 383 } 384}