1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.frontend.FtqPtr 19 20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 21 with HasCircularQueuePtrHelper 22{ 23 val csrIn = io.csrio.get 24 val csrOut = io.csrio.get 25 val csrToDecode = io.csrToDecode.get 26 27 val setFsDirty = csrIn.fpu.dirty_fs 28 val setFflags = csrIn.fpu.fflags 29 30 val setVsDirty = csrIn.vpu.dirty_vs 31 val setVstart = csrIn.vpu.set_vstart 32 val setVtype = csrIn.vpu.set_vtype 33 val setVxsat = csrIn.vpu.set_vxsat 34 val vlFromPreg = csrIn.vpu.vl 35 36 val flushPipe = Wire(Bool()) 37 val flush = io.flush.valid 38 39 val (valid, src1, imm, func) = ( 40 io.in.valid, 41 io.in.bits.data.src(0), 42 io.in.bits.data.imm(Imm_Z().len - 1, 0), 43 io.in.bits.ctrl.fuOpType 44 ) 45 46 // split imm/src1/rd from IMM_Z: src1/rd for tval 47 val addr = Imm_Z().getCSRAddr(imm) 48 val rd = Imm_Z().getRD(imm) 49 val rs1 = Imm_Z().getRS1(imm) 50 val imm5 = Imm_Z().getImm5(imm) 51 val csri = ZeroExt(imm5, XLEN) 52 53 import CSRConst._ 54 55 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 56 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 57 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 58 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 59 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 60 private val isWfi = CSROpType.isWfi(func) 61 private val isCSRAcc = CSROpType.isCsrAccess(func) 62 63 val csrMod = Module(new NewCSR) 64 val trapInstMod = Module(new TrapInstMod) 65 66 private val privState = csrMod.io.status.privState 67 // The real reg value in CSR, with no read mask 68 private val regOut = csrMod.io.out.bits.regOut 69 private val src = Mux(CSROpType.needImm(func), csri, src1) 70 private val wdata = LookupTree(func, Seq( 71 CSROpType.wrt -> src1, 72 CSROpType.set -> (regOut | src1), 73 CSROpType.clr -> (regOut & (~src1).asUInt), 74 CSROpType.wrti -> csri, 75 CSROpType.seti -> (regOut | csri), 76 CSROpType.clri -> (regOut & (~csri).asUInt), 77 )) 78 79 private val csrAccess = valid && CSROpType.isCsrAccess(func) 80 private val csrWen = valid && ( 81 CSROpType.isCSRRW(func) || 82 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 83 ) 84 private val csrRen = valid && ( 85 CSROpType.isCSRRW(func) && rd =/= 0.U || 86 CSROpType.isCSRRSorRC(func) 87 ) 88 89 csrMod.io.in match { 90 case in => 91 in.valid := valid 92 in.bits.wen := csrWen 93 in.bits.ren := csrRen 94 in.bits.op := CSROpType.getCSROp(func) 95 in.bits.addr := addr 96 in.bits.src := src 97 in.bits.wdata := wdata 98 in.bits.mret := isMret 99 in.bits.sret := isSret 100 in.bits.dret := isDret 101 } 102 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 103 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 104 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 105 106 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 107 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 108 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 109 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 110 // Todo: shrink the width of trap vector. 111 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 112 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 113 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 114 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 115 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 116 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 117 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 118 119 csrMod.io.fromRob.commit.fflags := setFflags 120 csrMod.io.fromRob.commit.fsDirty := setFsDirty 121 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 122 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 123 csrMod.io.fromRob.commit.vsDirty := setVsDirty 124 csrMod.io.fromRob.commit.vstart := setVstart 125 csrMod.io.fromRob.commit.vl := vlFromPreg 126 // Todo: correct vtype 127 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 128 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 129 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 130 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 131 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 132 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 133 134 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 135 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 136 137 csrMod.io.perf := csrIn.perf 138 139 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 140 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 141 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 142 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 143 csrMod.platformIRP.STIP := false.B 144 csrMod.platformIRP.VSEIP := false.B // Todo 145 csrMod.platformIRP.VSTIP := false.B // Todo 146 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 147 148 csrMod.io.fromTop.hartId := io.csrin.get.hartId 149 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 150 private val csrModOutValid = csrMod.io.out.valid 151 private val csrModOut = csrMod.io.out.bits 152 153 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 154 trapInstMod.io.fromRob.flush.valid := io.flush.valid 155 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 156 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 157 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 158 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 159 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 160 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 161 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 162 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 163 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 164 case t => 165 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 166 }) 167 168 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 169 imsic.i.hartId := io.csrin.get.hartId 170 imsic.i.msiInfo := io.csrin.get.msiInfo 171 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 172 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 173 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 174 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 175 imsic.i.csr.vgein := csrMod.toAIA.vgein 176 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 177 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 178 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 179 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 180 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 181 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 182 183 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 184 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 185 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 186 csrMod.fromAIA.meip := imsic.o.meip 187 csrMod.fromAIA.seip := imsic.o.seip 188 csrMod.fromAIA.vseip := imsic.o.vseip 189 csrMod.fromAIA.mtopei := imsic.o.mtopei 190 csrMod.fromAIA.stopei := imsic.o.stopei 191 csrMod.fromAIA.vstopei := imsic.o.vstopei 192 193 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 194 195 exceptionVec(EX_BP ) := isEbreak 196 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 197 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 198 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 199 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 200 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 201 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 202 203 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 204 205 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 206 val isXRetFlag = RegInit(false.B) 207 isXRetFlag := Mux1H(Seq( 208 DelayN(flush, 5) -> false.B, 209 isXRet -> true.B, 210 )) 211 212 flushPipe := csrMod.io.out.bits.flushPipe 213 214 // tlb 215 val tlb = Wire(new TlbCsrBundle) 216 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 217 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 218 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 219 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 220 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 221 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 222 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 223 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 224 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 225 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 226 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 227 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 228 229 // expose several csr bits for tlb 230 tlb.priv.mxr := csrMod.io.tlb.mxr 231 tlb.priv.sum := csrMod.io.tlb.sum 232 tlb.priv.vmxr := csrMod.io.tlb.vmxr 233 tlb.priv.vsum := csrMod.io.tlb.vsum 234 tlb.priv.spvp := csrMod.io.tlb.spvp 235 tlb.priv.virt := csrMod.io.tlb.dvirt 236 tlb.priv.imode := csrMod.io.tlb.imode 237 tlb.priv.dmode := csrMod.io.tlb.dmode 238 239 io.in.ready := true.B // Todo: Async read imsic may block CSR 240 io.out.valid := csrModOutValid 241 io.out.bits.ctrl.exceptionVec.get := exceptionVec 242 io.out.bits.ctrl.flushPipe.get := flushPipe 243 io.out.bits.res.data := csrMod.io.out.bits.rData 244 245 io.out.bits.res.redirect.get.valid := isXRet 246 val redirect = io.out.bits.res.redirect.get.bits 247 redirect := 0.U.asTypeOf(redirect) 248 redirect.level := RedirectLevel.flushAfter 249 redirect.robIdx := io.in.bits.ctrl.robIdx 250 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 251 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 252 redirect.cfiUpdate.predTaken := true.B 253 redirect.cfiUpdate.taken := true.B 254 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc 255 // Only mispred will send redirect to frontend 256 redirect.cfiUpdate.isMisPred := true.B 257 258 connect0LatencyCtrlSingal 259 260 // Todo: summerize all difftest skip condition 261 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 262 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 263 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 264 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 265 266 csrOut.isXRet := isXRetFlag 267 268 csrOut.trapTarget := csrMod.io.out.bits.targetPc 269 csrOut.interrupt := csrMod.io.status.interrupt 270 csrOut.wfi_event := csrMod.io.status.wfiEvent 271 272 csrOut.tlb := tlb 273 274 csrOut.debugMode := csrMod.io.status.debugMode 275 276 csrOut.customCtrl match { 277 case custom => 278 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 279 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 280 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 281 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 282 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 283 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 284 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 285 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 286 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 287 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 288 // ICache 289 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 290 // Load violation predictor 291 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 292 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 293 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 294 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 295 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 296 // Branch predictor 297 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 298 // Memory Block 299 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 300 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 301 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 302 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 303 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 304 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 305 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 306 // Rename 307 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 308 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 309 // distribute csr write signal 310 // write to frontend and memory 311 custom.distribute_csr.w.valid := csrWen 312 custom.distribute_csr.w.bits.addr := addr 313 custom.distribute_csr.w.bits.data := wdata 314 // rename single step 315 custom.singlestep := csrMod.io.status.singleStepFlag 316 // trigger 317 custom.frontend_trigger := csrMod.io.status.frontendTrigger 318 custom.mem_trigger := csrMod.io.status.memTrigger 319 // virtual mode 320 custom.virtMode := csrMod.io.status.privState.V.asBool 321 } 322 323 csrToDecode := csrMod.io.toDecode 324} 325 326class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 327 val hartId = Input(UInt(8.W)) 328 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 329 val clintTime = Input(ValidIO(UInt(64.W))) 330 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 331} 332 333class CSRToDecode(implicit p: Parameters) extends XSBundle { 334 val illegalInst = new Bundle { 335 /** 336 * illegal sfence.vma, sinval.vma 337 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 338 */ 339 val sfenceVMA = Bool() 340 341 /** 342 * illegal sfence.w.inval sfence.inval.ir 343 * raise EX_II when isModeHU 344 */ 345 val sfencePart = Bool() 346 347 /** 348 * illegal hfence.gvma, hinval.gvma 349 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 350 * the condition is the same as sfenceVMA 351 */ 352 val hfenceGVMA = Bool() 353 354 /** 355 * illegal hfence.vvma, hinval.vvma 356 * raise EX_II when isModeHU 357 */ 358 val hfenceVVMA = Bool() 359 360 /** 361 * illegal hlv, hlvx, and hsv 362 * raise EX_II when isModeHU && hstatus.HU=0 363 */ 364 val hlsv = Bool() 365 366 /** 367 * decode all fp inst or all vecfp inst 368 * raise EX_II when FS=Off 369 */ 370 val fsIsOff = Bool() 371 372 /** 373 * decode all vec inst 374 * raise EX_II when VS=Off 375 */ 376 val vsIsOff = Bool() 377 378 /** 379 * illegal wfi 380 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 381 */ 382 val wfi = Bool() 383 384 /** 385 * frm reserved 386 * raise EX_II when frm.data > 4 387 */ 388 val frm = Bool() 389 } 390 val virtualInst = new Bundle { 391 /** 392 * illegal sfence.vma, svinval.vma 393 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 394 */ 395 val sfenceVMA = Bool() 396 397 /** 398 * illegal sfence.w.inval sfence.inval.ir 399 * raise EX_VI when isModeVU 400 */ 401 val sfencePart = Bool() 402 403 /** 404 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 405 * raise EX_VI when isModeVS || isModeVU 406 */ 407 val hfence = Bool() 408 409 /** 410 * illegal hlv, hlvx, and hsv 411 * raise EX_VI when isModeVS || isModeVU 412 */ 413 val hlsv = Bool() 414 415 /** 416 * illegal wfi 417 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 418 */ 419 val wfi = Bool() 420 } 421}