1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 14import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 15 16class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 17{ 18 val csrIn = io.csrio.get 19 val csrOut = io.csrio.get 20 21 val setFsDirty = csrIn.fpu.dirty_fs 22 val setFflags = csrIn.fpu.fflags 23 val setVsDirty = csrIn.vpu.dirty_vs 24 val setVxsat = csrIn.vpu.vxsat 25 val setVstart = csrIn.vpu.set_vstart 26 val setVl = csrIn.vpu.set_vl 27 val setVtype = 0.U.asTypeOf(csrIn.vpu.set_vtype) 28 29 val flushPipe = Wire(Bool()) 30 val flush = io.flush.valid 31 32 val (valid, src1, src2, func) = ( 33 io.in.valid, 34 io.in.bits.data.src(0), 35 io.in.bits.data.imm, 36 io.in.bits.ctrl.fuOpType 37 ) 38 39 // split imm from IMM_Z 40 val addr = src2(11, 0) 41 val csri = ZeroExt(src2(16, 12), XLEN) 42 43 import CSRConst._ 44 45 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 46 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 47 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 48 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 49 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 50 private val isWfi = CSROpType.isWfi(func) 51 private val isCSRAcc = CSROpType.isCsrAccess(func) 52 53 val csrMod = Module(new NewCSR) 54 55 private val privState = csrMod.io.out.privState 56 // The real reg value in CSR, with no read mask 57 private val regOut = csrMod.io.out.regOut 58 // The read data with read mask 59 private val rdata = csrMod.io.out.rData 60 private val wdata = LookupTree(func, Seq( 61 CSROpType.wrt -> src1, 62 CSROpType.set -> (regOut | src1), 63 CSROpType.clr -> (regOut & (~src1).asUInt), 64 CSROpType.wrti -> csri, 65 CSROpType.seti -> (regOut | csri), 66 CSROpType.clri -> (regOut & (~csri).asUInt), 67 )) 68 69 private val csrAccess = valid && CSROpType.isCsrAccess(func) 70 private val csrWen = valid && CSROpType.notReadOnly(func) 71 72 csrMod.io.in match { 73 case in => 74 in.wen := csrWen 75 in.ren := csrAccess 76 in.addr := addr 77 in.wdata := wdata 78 } 79 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 80 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 81 82 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 83 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 84 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 85 // Todo: shrink the width of trap vector. 86 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 87 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 88 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 89 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 90 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 91 csrMod.io.fromRob.trap.bits.triggerCf := csrIn.exception.bits.trigger 92 93 csrMod.io.fromRob.commit.fflags := setFflags 94 csrMod.io.fromRob.commit.fsDirty := setFsDirty 95 csrMod.io.fromRob.commit.vxsat.valid := setVxsat 96 csrMod.io.fromRob.commit.vxsat.bits := setVxsat 97 csrMod.io.fromRob.commit.vsDirty := setVsDirty 98 csrMod.io.fromRob.commit.vstart := setVstart 99 csrMod.io.fromRob.commit.vl := setVl 100 // Todo: correct vtype 101 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 102 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 103 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 104 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 105 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 106 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 107 108 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 109 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 110 111 csrMod.io.mret := isMret && valid 112 csrMod.io.sret := isSret && valid 113 csrMod.io.dret := isDret && valid 114 csrMod.io.wfi := isWfi && valid 115 csrMod.io.ebreak := isEbreak && valid 116 117 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 118 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 119 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 120 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 121 csrMod.platformIRP.VSEIP := false.B // Todo 122 csrMod.platformIRP.VSTIP := false.B // Todo 123 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 124 125 csrMod.io.fromTop.hartId := io.csrin.get.hartId 126 127 private val imsic = Module(new IMSIC) 128 imsic.i.hartId := io.csrin.get.hartId 129 imsic.i.msiInfo := io.csrin.get.msiInfo 130 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 131 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 132 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 133 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 134 imsic.i.csr.vgein := csrMod.toAIA.vgein 135 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 136 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 137 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 138 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 139 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 140 141 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 142 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 143 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 144 csrMod.fromAIA.mtopei.valid := imsic.o.mtopei.valid 145 csrMod.fromAIA.stopei.valid := imsic.o.stopei.valid 146 csrMod.fromAIA.vstopei.valid := imsic.o.vstopei.valid 147 csrMod.fromAIA.mtopei.bits := imsic.o.mtopei.bits 148 csrMod.fromAIA.stopei.bits := imsic.o.stopei.bits 149 csrMod.fromAIA.vstopei.bits := imsic.o.vstopei.bits 150 151 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 152 import ExceptionNO._ 153 exceptionVec(EX_BP ) := isEbreak 154 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 155 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 156 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 157 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 158 exceptionVec(EX_II ) := csrMod.io.out.EX_II 159 exceptionVec(EX_VI ) := csrMod.io.out.EX_VI 160 161 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 162 163 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 164 val isXRetFlag = RegInit(false.B) 165 isXRetFlag := Mux1H(Seq( 166 DelayN(flush, 5) -> false.B, 167 isXRet -> true.B, 168 )) 169 170 flushPipe := csrMod.io.out.flushPipe 171 172 // tlb 173 val tlb = Wire(new TlbCsrBundle) 174 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 175 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 176 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 177 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 178 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 179 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 180 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 181 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 182 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 183 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 184 tlb.hgatp.asid := csrMod.io.tlb.hgatp.VMID.asUInt 185 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 186 187 // expose several csr bits for tlb 188 tlb.priv.mxr := csrMod.io.tlb.mxr 189 tlb.priv.sum := csrMod.io.tlb.sum 190 tlb.priv.vmxr := csrMod.io.tlb.vmxr 191 tlb.priv.vsum := csrMod.io.tlb.vsum 192 tlb.priv.spvp := csrMod.io.tlb.spvp 193 tlb.priv.virt := csrMod.io.out.privState.V.asBool 194 tlb.priv.imode := csrMod.io.tlb.imode 195 tlb.priv.dmode := csrMod.io.tlb.dmode 196 197 io.in.ready := true.B // Todo: Async read imsic may block CSR 198 io.out.valid := valid 199 io.out.bits.ctrl.exceptionVec.get := exceptionVec 200 io.out.bits.ctrl.flushPipe.get := flushPipe 201 io.out.bits.res.data := csrMod.io.out.rData 202 203 io.out.bits.res.redirect.get.valid := isXRet 204 val redirect = io.out.bits.res.redirect.get.bits 205 redirect := 0.U.asTypeOf(redirect) 206 redirect.level := RedirectLevel.flushAfter 207 redirect.robIdx := io.in.bits.ctrl.robIdx 208 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 209 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 210 redirect.cfiUpdate.predTaken := true.B 211 redirect.cfiUpdate.taken := true.B 212 redirect.cfiUpdate.target := csrMod.io.out.targetPc 213 // Only mispred will send redirect to frontend 214 redirect.cfiUpdate.isMisPred := true.B 215 216 connect0LatencyCtrlSingal 217 218 // Todo: summerize all difftest skip condition 219 csrOut.isPerfCnt := csrMod.io.out.isPerfCnt && valid && func =/= CSROpType.jmp 220 csrOut.fpu.frm := csrMod.io.out.fpState.frm.asUInt 221 csrOut.vpu.vstart := csrMod.io.out.vecState.vstart.asUInt 222 csrOut.vpu.vxsat := csrMod.io.out.vecState.vxsat.asUInt 223 csrOut.vpu.vxrm := csrMod.io.out.vecState.vxrm.asUInt 224 csrOut.vpu.vcsr := csrMod.io.out.vecState.vcsr.asUInt 225 csrOut.vpu.vl := csrMod.io.out.vecState.vl.asUInt 226 csrOut.vpu.vtype := csrMod.io.out.vecState.vtype.asUInt 227 csrOut.vpu.vlenb := csrMod.io.out.vecState.vlenb.asUInt 228 csrOut.vpu.vill := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VILL.asUInt 229 csrOut.vpu.vma := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VMA.asUInt 230 csrOut.vpu.vta := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VTA.asUInt 231 csrOut.vpu.vsew := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VSEW.asUInt 232 csrOut.vpu.vlmul := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VLMUL.asUInt 233 234 csrOut.isXRet := isXRetFlag 235 236 csrOut.trapTarget := csrMod.io.out.targetPc 237 csrOut.interrupt := csrMod.io.out.interrupt 238 csrOut.wfi_event := csrMod.io.out.wfiEvent 239 240 csrOut.tlb := tlb 241 242 csrOut.debugMode := csrMod.io.out.debugMode 243 244 // Todo: this bundle should be used in decode. 245 // Todo: check permission in decode stage, pass tvm and vtvm only 246 csrOut.disableSfence := Mux( 247 csrMod.io.out.tvm, 248 csrMod.io.out.privState < PrivState.ModeM, 249 csrMod.io.out.privState.PRVM < PrivMode.S 250 ) 251 csrOut.disableHfencev := DontCare // Todo 252 csrOut.disableHfenceg := DontCare // Todo 253 254 csrOut.customCtrl match { 255 case custom => 256 custom.l1I_pf_enable := csrMod.io.out.custom.l1I_pf_enable 257 custom.l2_pf_enable := csrMod.io.out.custom.l2_pf_enable 258 custom.l1D_pf_enable := csrMod.io.out.custom.l1D_pf_enable 259 custom.l1D_pf_train_on_hit := csrMod.io.out.custom.l1D_pf_train_on_hit 260 custom.l1D_pf_enable_agt := csrMod.io.out.custom.l1D_pf_enable_agt 261 custom.l1D_pf_enable_pht := csrMod.io.out.custom.l1D_pf_enable_pht 262 custom.l1D_pf_active_threshold := csrMod.io.out.custom.l1D_pf_active_threshold 263 custom.l1D_pf_active_stride := csrMod.io.out.custom.l1D_pf_active_stride 264 custom.l1D_pf_enable_stride := csrMod.io.out.custom.l1D_pf_enable_stride 265 custom.l2_pf_store_only := csrMod.io.out.custom.l2_pf_store_only 266 // ICache 267 custom.icache_parity_enable := csrMod.io.out.custom.icache_parity_enable 268 // Load violation predictor 269 custom.lvpred_disable := csrMod.io.out.custom.lvpred_disable 270 custom.no_spec_load := csrMod.io.out.custom.no_spec_load 271 custom.storeset_wait_store := csrMod.io.out.custom.storeset_wait_store 272 custom.storeset_no_fast_wakeup := csrMod.io.out.custom.storeset_no_fast_wakeup 273 custom.lvpred_timeout := csrMod.io.out.custom.lvpred_timeout 274 // Branch predictor 275 custom.bp_ctrl := csrMod.io.out.custom.bp_ctrl 276 // Memory Block 277 custom.sbuffer_threshold := csrMod.io.out.custom.sbuffer_threshold 278 custom.ldld_vio_check_enable := csrMod.io.out.custom.ldld_vio_check_enable 279 custom.soft_prefetch_enable := csrMod.io.out.custom.soft_prefetch_enable 280 custom.cache_error_enable := csrMod.io.out.custom.cache_error_enable 281 custom.uncache_write_outstanding_enable := csrMod.io.out.custom.uncache_write_outstanding_enable 282 // Rename 283 custom.fusion_enable := csrMod.io.out.custom.fusion_enable 284 custom.wfi_enable := csrMod.io.out.custom.wfi_enable 285 // distribute csr write signal 286 // write to frontend and memory 287 custom.distribute_csr.w.valid := csrWen 288 custom.distribute_csr.w.bits.addr := addr 289 custom.distribute_csr.w.bits.data := wdata 290 // rename single step 291 custom.singlestep := csrMod.io.out.singleStepFlag 292 // trigger 293 custom.frontend_trigger.tUpdate.valid := csrMod.io.out.frontendTrigger.tUpdate.valid 294 custom.frontend_trigger.tUpdate.bits.addr := csrMod.io.out.frontendTrigger.tUpdate.bits.addr 295 custom.frontend_trigger.tUpdate.bits.tdata := csrMod.io.out.frontendTrigger.tUpdate.bits.tdata 296 custom.frontend_trigger.tEnableVec := csrMod.io.out.frontendTrigger.tEnableVec 297 custom.mem_trigger.tUpdate.valid := csrMod.io.out.memTrigger.tUpdate.valid 298 custom.mem_trigger.tUpdate.bits.addr := csrMod.io.out.memTrigger.tUpdate.bits.addr 299 custom.mem_trigger.tUpdate.bits.tdata := csrMod.io.out.memTrigger.tUpdate.bits.tdata 300 custom.mem_trigger.tEnableVec := csrMod.io.out.memTrigger.tEnableVec 301 // virtual mode 302 custom.virtMode := csrMod.io.out.privState.V.asBool 303 } 304} 305 306class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 307 val hartId = Input(UInt(8.W)) 308 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 309}