1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.Bundles.TrapInstInfo 14import xiangshan.backend.decode.Imm_Z 15import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 16import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 17import xiangshan.frontend.FtqPtr 18 19class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 20 with HasCircularQueuePtrHelper 21{ 22 val csrIn = io.csrio.get 23 val csrOut = io.csrio.get 24 val csrToDecode = io.csrToDecode.get 25 26 val setFsDirty = csrIn.fpu.dirty_fs 27 val setFflags = csrIn.fpu.fflags 28 29 val setVsDirty = csrIn.vpu.dirty_vs 30 val setVstart = csrIn.vpu.set_vstart 31 val setVtype = csrIn.vpu.set_vtype 32 val setVxsat = csrIn.vpu.set_vxsat 33 val vlFromPreg = csrIn.vpu.vl 34 35 val flushPipe = Wire(Bool()) 36 val flush = io.flush.valid 37 38 val (valid, src1, imm, func) = ( 39 io.in.valid, 40 io.in.bits.data.src(0), 41 io.in.bits.data.imm(Imm_Z().len - 1, 0), 42 io.in.bits.ctrl.fuOpType 43 ) 44 45 // split imm/src1/rd from IMM_Z: src1/rd for tval 46 val addr = Imm_Z().getCSRAddr(imm) 47 val rd = Imm_Z().getRD(imm) 48 val rs1 = Imm_Z().getRS1(imm) 49 val imm5 = Imm_Z().getImm5(imm) 50 val csri = ZeroExt(imm5, XLEN) 51 52 import CSRConst._ 53 54 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 55 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 56 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 57 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 58 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 59 private val isWfi = CSROpType.isWfi(func) 60 private val isCSRAcc = CSROpType.isCsrAccess(func) 61 62 val csrMod = Module(new NewCSR) 63 val trapInstMod = Module(new TrapInstMod) 64 65 private val privState = csrMod.io.status.privState 66 // The real reg value in CSR, with no read mask 67 private val regOut = csrMod.io.out.bits.regOut 68 private val src = Mux(CSROpType.needImm(func), csri, src1) 69 private val wdata = LookupTree(func, Seq( 70 CSROpType.wrt -> src1, 71 CSROpType.set -> (regOut | src1), 72 CSROpType.clr -> (regOut & (~src1).asUInt), 73 CSROpType.wrti -> csri, 74 CSROpType.seti -> (regOut | csri), 75 CSROpType.clri -> (regOut & (~csri).asUInt), 76 )) 77 78 private val csrAccess = valid && CSROpType.isCsrAccess(func) 79 private val csrWen = valid && ( 80 CSROpType.isCSRRW(func) || 81 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 82 ) 83 private val csrRen = valid && ( 84 CSROpType.isCSRRW(func) && rd =/= 0.U || 85 CSROpType.isCSRRSorRC(func) 86 ) 87 88 csrMod.io.in match { 89 case in => 90 in.valid := valid 91 in.bits.wen := csrWen 92 in.bits.ren := csrRen 93 in.bits.op := CSROpType.getCSROp(func) 94 in.bits.addr := addr 95 in.bits.src := src 96 in.bits.wdata := wdata 97 in.bits.mret := isMret 98 in.bits.sret := isSret 99 in.bits.dret := isDret 100 } 101 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 102 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 103 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 104 105 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 106 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 107 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 108 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 109 // Todo: shrink the width of trap vector. 110 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 111 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 112 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 113 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 114 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 115 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 116 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 117 118 csrMod.io.fromRob.commit.fflags := setFflags 119 csrMod.io.fromRob.commit.fsDirty := setFsDirty 120 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 121 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 122 csrMod.io.fromRob.commit.vsDirty := setVsDirty 123 csrMod.io.fromRob.commit.vstart := setVstart 124 csrMod.io.fromRob.commit.vl := vlFromPreg 125 // Todo: correct vtype 126 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 127 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 128 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 129 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 130 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 131 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 132 133 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 134 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 135 136 csrMod.io.perf := csrIn.perf 137 138 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 139 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 140 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 141 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 142 csrMod.platformIRP.STIP := false.B 143 csrMod.platformIRP.VSEIP := false.B // Todo 144 csrMod.platformIRP.VSTIP := false.B // Todo 145 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 146 147 csrMod.io.fromTop.hartId := io.csrin.get.hartId 148 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 149 private val csrModOutValid = csrMod.io.out.valid 150 private val csrModOut = csrMod.io.out.bits 151 152 trapInstMod.io.fromDecode.trapInstInfo := io.csrin.get.trapInstInfo 153 trapInstMod.io.fromRob.flush.valid := io.flush.valid 154 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 155 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 156 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 157 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 158 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 159 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 160 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 161 // Clear trap instruction when any trap occurs. 162 trapInstMod.io.readClear := csrMod.io.fromRob.trap.valid 163 164 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 165 imsic.i.hartId := io.csrin.get.hartId 166 imsic.i.msiInfo := io.csrin.get.msiInfo 167 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 168 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 169 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 170 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 171 imsic.i.csr.vgein := csrMod.toAIA.vgein 172 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 173 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 174 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 175 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 176 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 177 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 178 179 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 180 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 181 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 182 csrMod.fromAIA.meip := imsic.o.meip 183 csrMod.fromAIA.seip := imsic.o.seip 184 csrMod.fromAIA.vseip := imsic.o.vseip 185 csrMod.fromAIA.mtopei := imsic.o.mtopei 186 csrMod.fromAIA.stopei := imsic.o.stopei 187 csrMod.fromAIA.vstopei := imsic.o.vstopei 188 189 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 190 import ExceptionNO._ 191 exceptionVec(EX_BP ) := isEbreak 192 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 193 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 194 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 195 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 196 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 197 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 198 199 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 200 201 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 202 val isXRetFlag = RegInit(false.B) 203 isXRetFlag := Mux1H(Seq( 204 DelayN(flush, 5) -> false.B, 205 isXRet -> true.B, 206 )) 207 208 flushPipe := csrMod.io.out.bits.flushPipe 209 210 // tlb 211 val tlb = Wire(new TlbCsrBundle) 212 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 213 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 214 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 215 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 216 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 217 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 218 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 219 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 220 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 221 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 222 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 223 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 224 225 // expose several csr bits for tlb 226 tlb.priv.mxr := csrMod.io.tlb.mxr 227 tlb.priv.sum := csrMod.io.tlb.sum 228 tlb.priv.vmxr := csrMod.io.tlb.vmxr 229 tlb.priv.vsum := csrMod.io.tlb.vsum 230 tlb.priv.spvp := csrMod.io.tlb.spvp 231 tlb.priv.virt := csrMod.io.tlb.dvirt 232 tlb.priv.imode := csrMod.io.tlb.imode 233 tlb.priv.dmode := csrMod.io.tlb.dmode 234 235 io.in.ready := true.B // Todo: Async read imsic may block CSR 236 io.out.valid := csrModOutValid 237 io.out.bits.ctrl.exceptionVec.get := exceptionVec 238 io.out.bits.ctrl.flushPipe.get := flushPipe 239 io.out.bits.res.data := csrMod.io.out.bits.rData 240 241 io.out.bits.res.redirect.get.valid := isXRet 242 val redirect = io.out.bits.res.redirect.get.bits 243 redirect := 0.U.asTypeOf(redirect) 244 redirect.level := RedirectLevel.flushAfter 245 redirect.robIdx := io.in.bits.ctrl.robIdx 246 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 247 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 248 redirect.cfiUpdate.predTaken := true.B 249 redirect.cfiUpdate.taken := true.B 250 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc 251 // Only mispred will send redirect to frontend 252 redirect.cfiUpdate.isMisPred := true.B 253 254 connect0LatencyCtrlSingal 255 256 // Todo: summerize all difftest skip condition 257 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 258 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 259 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 260 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 261 262 csrOut.isXRet := isXRetFlag 263 264 csrOut.trapTarget := csrMod.io.out.bits.targetPc 265 csrOut.interrupt := csrMod.io.status.interrupt 266 csrOut.wfi_event := csrMod.io.status.wfiEvent 267 268 csrOut.tlb := tlb 269 270 csrOut.debugMode := csrMod.io.status.debugMode 271 272 csrOut.customCtrl match { 273 case custom => 274 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 275 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 276 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 277 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 278 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 279 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 280 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 281 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 282 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 283 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 284 // ICache 285 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 286 // Load violation predictor 287 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 288 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 289 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 290 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 291 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 292 // Branch predictor 293 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 294 // Memory Block 295 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 296 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 297 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 298 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 299 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 300 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 301 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 302 // Rename 303 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 304 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 305 // distribute csr write signal 306 // write to frontend and memory 307 custom.distribute_csr.w.valid := csrWen 308 custom.distribute_csr.w.bits.addr := addr 309 custom.distribute_csr.w.bits.data := wdata 310 // rename single step 311 custom.singlestep := csrMod.io.status.singleStepFlag 312 // trigger 313 custom.frontend_trigger := csrMod.io.status.frontendTrigger 314 custom.mem_trigger := csrMod.io.status.memTrigger 315 // virtual mode 316 custom.virtMode := csrMod.io.status.privState.V.asBool 317 } 318 319 csrToDecode := csrMod.io.toDecode 320} 321 322class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 323 val hartId = Input(UInt(8.W)) 324 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 325 val clintTime = Input(ValidIO(UInt(64.W))) 326 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 327} 328 329class CSRToDecode(implicit p: Parameters) extends XSBundle { 330 val illegalInst = new Bundle { 331 /** 332 * illegal sfence.vma, sinval.vma 333 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 334 */ 335 val sfenceVMA = Bool() 336 337 /** 338 * illegal sfence.w.inval sfence.inval.ir 339 * raise EX_II when isModeHU 340 */ 341 val sfencePart = Bool() 342 343 /** 344 * illegal hfence.gvma, hinval.gvma 345 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 346 * the condition is the same as sfenceVMA 347 */ 348 val hfenceGVMA = Bool() 349 350 /** 351 * illegal hfence.vvma, hinval.vvma 352 * raise EX_II when isModeHU 353 */ 354 val hfenceVVMA = Bool() 355 356 /** 357 * illegal hlv, hlvx, and hsv 358 * raise EX_II when isModeHU && hstatus.HU=0 359 */ 360 val hlsv = Bool() 361 362 /** 363 * decode all fp inst or all vecfp inst 364 * raise EX_II when FS=Off 365 */ 366 val fsIsOff = Bool() 367 368 /** 369 * decode all vec inst 370 * raise EX_II when VS=Off 371 */ 372 val vsIsOff = Bool() 373 374 /** 375 * illegal wfi 376 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 377 */ 378 val wfi = Bool() 379 380 /** 381 * frm reserved 382 * raise EX_II when frm.data > 4 383 */ 384 val frm = Bool() 385 } 386 val virtualInst = new Bundle { 387 /** 388 * illegal sfence.vma, svinval.vma 389 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 390 */ 391 val sfenceVMA = Bool() 392 393 /** 394 * illegal sfence.w.inval sfence.inval.ir 395 * raise EX_VI when isModeVU 396 */ 397 val sfencePart = Bool() 398 399 /** 400 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 401 * raise EX_VI when isModeVS || isModeVU 402 */ 403 val hfence = Bool() 404 405 /** 406 * illegal hlv, hlvx, and hsv 407 * raise EX_VI when isModeVS || isModeVU 408 */ 409 val hlsv = Bool() 410 411 /** 412 * illegal wfi 413 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 414 */ 415 val wfi = Bool() 416 } 417}