1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 14import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 15 16class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 17{ 18 val csrIn = io.csrio.get 19 val csrOut = io.csrio.get 20 21 val setFsDirty = csrIn.fpu.dirty_fs 22 val setFflags = csrIn.fpu.fflags 23 val setVsDirty = csrIn.vpu.dirty_vs 24 val setVxsat = csrIn.vpu.vxsat 25 val setVstart = csrIn.vpu.set_vstart 26 val setVl = csrIn.vpu.set_vl 27 val setVtype = 0.U.asTypeOf(csrIn.vpu.set_vtype) 28 29 val flushPipe = Wire(Bool()) 30 val flush = io.flush.valid 31 32 val (valid, src1, src2, func) = ( 33 io.in.valid, 34 io.in.bits.data.src(0), 35 io.in.bits.data.imm, 36 io.in.bits.ctrl.fuOpType 37 ) 38 39 // split imm from IMM_Z 40 val addr = src2(11, 0) 41 val csri = src2(16, 12) 42 43 import CSRConst._ 44 45 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 46 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 47 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 48 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 49 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 50 private val isWfi = CSROpType.isWfi(func) 51 private val isCSRAcc = CSROpType.isCsrAccess(func) 52 53 val csrMod = Module(new NewCSR) 54 55 private val privState = csrMod.io.out.privState 56 // The real reg value in CSR, with no read mask 57 private val regOut = csrMod.io.out.regOut 58 // The read data with read mask 59 private val rdata = csrMod.io.out.rData 60 private val wdata = LookupTree(func, Seq( 61 CSROpType.wrt -> src1, 62 CSROpType.set -> (regOut | src1), 63 CSROpType.clr -> (regOut & (~src1).asUInt), 64 CSROpType.wrti -> csri, 65 CSROpType.seti -> (regOut | csri), 66 CSROpType.clri -> (regOut & (~csri).asUInt), 67 )) 68 69 private val csrAccess = valid && CSROpType.isCsrAccess(func) 70 private val csrWen = valid && CSROpType.notReadOnly(func) 71 72 csrMod.io.in match { 73 case in => 74 in.wen := csrWen 75 in.ren := csrAccess 76 in.addr := addr 77 in.wdata := wdata 78 } 79 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 80 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 81 82 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 83 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 84 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 85 // Todo: shrink the width of trap vector. 86 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 87 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 88 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 89 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 90 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 91 92 csrMod.io.fromRob.commit.fflags := setFflags 93 csrMod.io.fromRob.commit.fsDirty := setFsDirty 94 csrMod.io.fromRob.commit.vxsat.valid := setVxsat 95 csrMod.io.fromRob.commit.vxsat.bits := setVxsat 96 csrMod.io.fromRob.commit.vsDirty := setVsDirty 97 csrMod.io.fromRob.commit.vstart := setVstart 98 csrMod.io.fromRob.commit.vl := setVl 99 // Todo: correct vtype 100 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 101 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 102 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 103 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 104 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 105 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 106 107 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 108 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 109 110 csrMod.io.mret := isMret 111 csrMod.io.sret := isSret 112 csrMod.io.dret := isDret 113 csrMod.io.wfi := isWfi 114 115 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 116 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 117 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 118 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 119 csrMod.platformIRP.VSEIP := false.B // Todo 120 csrMod.platformIRP.VSTIP := false.B // Todo 121 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 122 123 csrMod.io.fromTop.hartId := io.csrin.get.hartId 124 125 private val imsic = Module(new IMSIC) 126 imsic.i.hartId := io.csrin.get.hartId 127 imsic.i.msiInfo := io.csrin.get.msiInfo 128 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 129 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 130 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 131 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 132 imsic.i.csr.vgein := csrMod.toAIA.vgein 133 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 134 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 135 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 136 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 137 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 138 139 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 140 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 141 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 142 csrMod.fromAIA.mtopei.valid := imsic.o.mtopei.valid 143 csrMod.fromAIA.stopei.valid := imsic.o.stopei.valid 144 csrMod.fromAIA.vstopei.valid := imsic.o.vstopei.valid 145 csrMod.fromAIA.mtopei.bits := imsic.o.mtopei.bits 146 csrMod.fromAIA.stopei.bits := imsic.o.stopei.bits 147 csrMod.fromAIA.vstopei.bits := imsic.o.vstopei.bits 148 149 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 150 import ExceptionNO._ 151 exceptionVec(EX_BP ) := isEbreak 152 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 153 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 154 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 155 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 156 exceptionVec(EX_II ) := csrMod.io.out.EX_II 157 //exceptionVec(EX_VI ) := csrMod.io.out.EX_VI // Todo: check other EX_VI 158 159 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 160 161 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 162 val isXRetFlag = RegInit(false.B) 163 isXRetFlag := Mux1H(Seq( 164 DelayN(flush, 5) -> false.B, 165 isXRet -> true.B, 166 )) 167 168 flushPipe := csrMod.io.out.flushPipe || isXRet // || frontendTriggerUpdate // Todo: trigger 169 170 // tlb 171 val tlb = Wire(new TlbCsrBundle) 172 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 173 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 174 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 175 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 176 // expose several csr bits for tlb 177 tlb.priv.mxr := csrMod.io.tlb.mxr 178 tlb.priv.sum := csrMod.io.tlb.sum 179 tlb.priv.imode := csrMod.io.tlb.imode 180 tlb.priv.dmode := csrMod.io.tlb.dmode 181 tlb.vsatp := DontCare // Todo 182 tlb.hgatp := DontCare // Todo 183 tlb.priv.vmxr := DontCare // Todo 184 tlb.priv.vsum := DontCare // Todo 185 tlb.priv.spvp := DontCare // Todo 186 tlb.priv.virt := csrMod.io.out.privState.V.asBool 187 188 io.in.ready := true.B // Todo: Async read imsic may block CSR 189 io.out.valid := valid 190 io.out.bits.ctrl.exceptionVec.get := exceptionVec 191 io.out.bits.ctrl.flushPipe.get := flushPipe 192 io.out.bits.res.data := csrMod.io.out.rData 193 connect0LatencyCtrlSingal 194 195 // Todo: summerize all difftest skip condition 196 csrOut.isPerfCnt := csrMod.io.out.isPerfCnt && valid && func =/= CSROpType.jmp 197 csrOut.fpu.frm := csrMod.io.out.fpState.frm.asUInt 198 csrOut.vpu.vstart := csrMod.io.out.vecState.vstart.asUInt 199 csrOut.vpu.vxsat := csrMod.io.out.vecState.vxsat.asUInt 200 csrOut.vpu.vxrm := csrMod.io.out.vecState.vxrm.asUInt 201 csrOut.vpu.vcsr := csrMod.io.out.vecState.vcsr.asUInt 202 csrOut.vpu.vl := csrMod.io.out.vecState.vl.asUInt 203 csrOut.vpu.vtype := csrMod.io.out.vecState.vtype.asUInt 204 csrOut.vpu.vlenb := csrMod.io.out.vecState.vlenb.asUInt 205 csrOut.vpu.vill := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VILL.asUInt 206 csrOut.vpu.vma := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VMA.asUInt 207 csrOut.vpu.vta := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VTA.asUInt 208 csrOut.vpu.vsew := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VSEW.asUInt 209 csrOut.vpu.vlmul := csrMod.io.out.vecState.vtype.asTypeOf(new CSRVTypeBundle).VLMUL.asUInt 210 211 csrOut.isXRet := isXRetFlag 212 213 csrOut.trapTarget := csrMod.io.out.targetPc 214 csrOut.interrupt := csrMod.io.out.interrupt 215 csrOut.wfi_event := csrMod.io.out.wfiEvent 216 217 csrOut.tlb := tlb 218 219 csrOut.debugMode := csrMod.io.out.debugMode 220 221 // Todo: this bundle should be used in decode. 222 // Todo: check permission in decode stage, pass tvm and vtvm only 223 csrOut.disableSfence := Mux( 224 csrMod.io.out.tvm, 225 csrMod.io.out.privState < PrivState.ModeM, 226 csrMod.io.out.privState.PRVM < PrivMode.S 227 ) 228 csrOut.disableHfencev := DontCare // Todo 229 csrOut.disableHfenceg := DontCare // Todo 230 231 csrOut.customCtrl match { 232 case custom => 233 custom.l1I_pf_enable := csrMod.io.out.custom.l1I_pf_enable 234 custom.l2_pf_enable := csrMod.io.out.custom.l2_pf_enable 235 custom.l1D_pf_enable := csrMod.io.out.custom.l1D_pf_enable 236 custom.l1D_pf_train_on_hit := csrMod.io.out.custom.l1D_pf_train_on_hit 237 custom.l1D_pf_enable_agt := csrMod.io.out.custom.l1D_pf_enable_agt 238 custom.l1D_pf_enable_pht := csrMod.io.out.custom.l1D_pf_enable_pht 239 custom.l1D_pf_active_threshold := csrMod.io.out.custom.l1D_pf_active_threshold 240 custom.l1D_pf_active_stride := csrMod.io.out.custom.l1D_pf_active_stride 241 custom.l1D_pf_enable_stride := csrMod.io.out.custom.l1D_pf_enable_stride 242 custom.l2_pf_store_only := csrMod.io.out.custom.l2_pf_store_only 243 // ICache 244 custom.icache_parity_enable := csrMod.io.out.custom.icache_parity_enable 245 // Labeled XiangShan 246 custom.dsid := csrMod.io.out.custom.dsid 247 // Load violation predictor 248 custom.lvpred_disable := csrMod.io.out.custom.lvpred_disable 249 custom.no_spec_load := csrMod.io.out.custom.no_spec_load 250 custom.storeset_wait_store := csrMod.io.out.custom.storeset_wait_store 251 custom.storeset_no_fast_wakeup := csrMod.io.out.custom.storeset_no_fast_wakeup 252 custom.lvpred_timeout := csrMod.io.out.custom.lvpred_timeout 253 // Branch predictor 254 custom.bp_ctrl := csrMod.io.out.custom.bp_ctrl 255 // Memory Block 256 custom.sbuffer_threshold := csrMod.io.out.custom.sbuffer_threshold 257 custom.ldld_vio_check_enable := csrMod.io.out.custom.ldld_vio_check_enable 258 custom.soft_prefetch_enable := csrMod.io.out.custom.soft_prefetch_enable 259 custom.cache_error_enable := csrMod.io.out.custom.cache_error_enable 260 custom.uncache_write_outstanding_enable := csrMod.io.out.custom.uncache_write_outstanding_enable 261 // Rename 262 custom.fusion_enable := csrMod.io.out.custom.fusion_enable 263 custom.wfi_enable := csrMod.io.out.custom.wfi_enable 264 // Decode 265 custom.svinval_enable := csrMod.io.out.custom.svinval_enable 266 // distribute csr write signal 267 // write to frontend and memory 268 custom.distribute_csr.w.valid := csrWen 269 custom.distribute_csr.w.bits.addr := addr 270 custom.distribute_csr.w.bits.data := wdata 271 // rename single step 272 custom.singlestep := csrMod.io.out.singleStepFlag 273 // trigger 274 custom.frontend_trigger.tUpdate.valid := false.B 275 custom.frontend_trigger.tUpdate.bits.addr := DontCare 276 custom.frontend_trigger.tUpdate.bits.tdata := DontCare 277 custom.frontend_trigger.tEnableVec := DontCare 278 custom.mem_trigger.tUpdate.valid := false.B 279 custom.mem_trigger.tUpdate.bits.addr := DontCare 280 custom.mem_trigger.tUpdate.bits.tdata := DontCare 281 custom.mem_trigger.tEnableVec := DontCare 282 // virtual mode 283 custom.virtMode := csrMod.io.out.privState.V.asBool 284 } 285} 286 287class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 288 val hartId = Input(UInt(8.W)) 289 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 290}