1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.frontend.FtqPtr 19 20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 21 with HasCircularQueuePtrHelper 22{ 23 val csrIn = io.csrio.get 24 val csrOut = io.csrio.get 25 val csrToDecode = io.csrToDecode.get 26 27 val setFsDirty = csrIn.fpu.dirty_fs 28 val setFflags = csrIn.fpu.fflags 29 30 val setVsDirty = csrIn.vpu.dirty_vs 31 val setVstart = csrIn.vpu.set_vstart 32 val setVtype = csrIn.vpu.set_vtype 33 val setVxsat = csrIn.vpu.set_vxsat 34 val vlFromPreg = csrIn.vpu.vl 35 36 val flushPipe = Wire(Bool()) 37 val flush = io.flush.valid 38 39 val (valid, src1, imm, func) = ( 40 io.in.valid, 41 io.in.bits.data.src(0), 42 io.in.bits.data.imm(Imm_Z().len - 1, 0), 43 io.in.bits.ctrl.fuOpType 44 ) 45 46 // split imm/src1/rd from IMM_Z: src1/rd for tval 47 val addr = Imm_Z().getCSRAddr(imm) 48 val rd = Imm_Z().getRD(imm) 49 val rs1 = Imm_Z().getRS1(imm) 50 val imm5 = Imm_Z().getImm5(imm) 51 val csri = ZeroExt(imm5, XLEN) 52 53 import CSRConst._ 54 55 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 56 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 57 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 58 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 59 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 60 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 61 private val isWfi = CSROpType.isWfi(func) 62 private val isCSRAcc = CSROpType.isCsrAccess(func) 63 64 val csrMod = Module(new NewCSR) 65 val trapInstMod = Module(new TrapInstMod) 66 val trapTvalMod = Module(new TrapTvalMod) 67 68 private val privState = csrMod.io.status.privState 69 // The real reg value in CSR, with no read mask 70 private val regOut = csrMod.io.out.bits.regOut 71 private val src = Mux(CSROpType.needImm(func), csri, src1) 72 private val wdata = LookupTree(func, Seq( 73 CSROpType.wrt -> src1, 74 CSROpType.set -> (regOut | src1), 75 CSROpType.clr -> (regOut & (~src1).asUInt), 76 CSROpType.wrti -> csri, 77 CSROpType.seti -> (regOut | csri), 78 CSROpType.clri -> (regOut & (~csri).asUInt), 79 )) 80 81 private val csrAccess = valid && CSROpType.isCsrAccess(func) 82 private val csrWen = valid && ( 83 CSROpType.isCSRRW(func) || 84 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 85 ) 86 private val csrRen = valid && ( 87 CSROpType.isCSRRW(func) && rd =/= 0.U || 88 CSROpType.isCSRRSorRC(func) 89 ) 90 91 csrMod.io.in match { 92 case in => 93 in.valid := valid 94 in.bits.wen := csrWen 95 in.bits.ren := csrRen 96 in.bits.op := CSROpType.getCSROp(func) 97 in.bits.addr := addr 98 in.bits.src := src 99 in.bits.wdata := wdata 100 in.bits.mret := isMret 101 in.bits.mnret := isMNret 102 in.bits.sret := isSret 103 in.bits.dret := isDret 104 } 105 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 106 csrMod.io.fetchMalTval := trapTvalMod.io.tval 107 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 108 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 109 110 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 111 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 112 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 113 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 114 // Todo: shrink the width of trap vector. 115 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 116 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 117 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 118 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 119 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 120 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 121 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 122 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 123 124 csrMod.io.fromRob.commit.fflags := setFflags 125 csrMod.io.fromRob.commit.fsDirty := setFsDirty 126 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 127 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 128 csrMod.io.fromRob.commit.vsDirty := setVsDirty 129 csrMod.io.fromRob.commit.vstart := setVstart 130 csrMod.io.fromRob.commit.vl := vlFromPreg 131 // Todo: correct vtype 132 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 133 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 134 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 135 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 136 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 137 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 138 139 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 140 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 141 142 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 143 144 csrMod.io.perf := csrIn.perf 145 146 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 147 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 148 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 149 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 150 csrMod.platformIRP.STIP := false.B 151 csrMod.platformIRP.VSEIP := false.B // Todo 152 csrMod.platformIRP.VSTIP := false.B // Todo 153 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 154 csrMod.nonMaskableIRP.NMI := csrIn.externalInterrupt.nmi.nmi 155 156 csrMod.io.fromTop.hartId := io.csrin.get.hartId 157 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 158 private val csrModOutValid = csrMod.io.out.valid 159 private val csrModOut = csrMod.io.out.bits 160 161 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 162 trapInstMod.io.fromRob.flush.valid := io.flush.valid 163 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 164 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 165 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 166 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 167 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 168 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 169 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 170 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 171 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 172 case t => 173 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 174 }) 175 176 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 177 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 178 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 179 trapTvalMod.io.fromCtrlBlock.flush := io.flush 180 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 181 182 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 183 imsic.i.hartId := io.csrin.get.hartId 184 imsic.i.msiInfo := io.csrin.get.msiInfo 185 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 186 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 187 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 188 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 189 imsic.i.csr.vgein := csrMod.toAIA.vgein 190 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 191 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 192 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 193 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 194 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 195 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 196 197 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 198 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 199 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 200 csrMod.fromAIA.meip := imsic.o.meip 201 csrMod.fromAIA.seip := imsic.o.seip 202 csrMod.fromAIA.vseip := imsic.o.vseip 203 csrMod.fromAIA.mtopei := imsic.o.mtopei 204 csrMod.fromAIA.stopei := imsic.o.stopei 205 csrMod.fromAIA.vstopei := imsic.o.vstopei 206 207 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 208 209 exceptionVec(EX_BP ) := isEbreak 210 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 211 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 212 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 213 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 214 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 215 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 216 217 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 218 219 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 220 val isXRetFlag = RegInit(false.B) 221 isXRetFlag := Mux1H(Seq( 222 DelayN(flush, 5) -> false.B, 223 isXRet -> true.B, 224 )) 225 226 flushPipe := csrMod.io.out.bits.flushPipe 227 228 // tlb 229 val tlb = Wire(new TlbCsrBundle) 230 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 231 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 232 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 233 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 234 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 235 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 236 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 237 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 238 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 239 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 240 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 241 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 242 243 // expose several csr bits for tlb 244 tlb.priv.mxr := csrMod.io.tlb.mxr 245 tlb.priv.sum := csrMod.io.tlb.sum 246 tlb.priv.vmxr := csrMod.io.tlb.vmxr 247 tlb.priv.vsum := csrMod.io.tlb.vsum 248 tlb.priv.spvp := csrMod.io.tlb.spvp 249 tlb.priv.virt := csrMod.io.tlb.dvirt 250 tlb.priv.imode := csrMod.io.tlb.imode 251 tlb.priv.dmode := csrMod.io.tlb.dmode 252 253 // Svpbmt extension enable 254 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 255 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 256 257 io.in.ready := true.B // Todo: Async read imsic may block CSR 258 io.out.valid := csrModOutValid 259 io.out.bits.ctrl.exceptionVec.get := exceptionVec 260 io.out.bits.ctrl.flushPipe.get := flushPipe 261 io.out.bits.res.data := csrMod.io.out.bits.rData 262 263 io.out.bits.res.redirect.get.valid := isXRet 264 val redirect = io.out.bits.res.redirect.get.bits 265 redirect := 0.U.asTypeOf(redirect) 266 redirect.level := RedirectLevel.flushAfter 267 redirect.robIdx := io.in.bits.ctrl.robIdx 268 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 269 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 270 redirect.cfiUpdate.predTaken := true.B 271 redirect.cfiUpdate.taken := true.B 272 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 273 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 274 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 275 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 276 // Only mispred will send redirect to frontend 277 redirect.cfiUpdate.isMisPred := true.B 278 279 connect0LatencyCtrlSingal 280 281 // Todo: summerize all difftest skip condition 282 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 283 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 284 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 285 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 286 287 csrOut.isXRet := isXRetFlag 288 289 csrOut.trapTarget := csrMod.io.out.bits.targetPc 290 csrOut.interrupt := csrMod.io.status.interrupt 291 csrOut.wfi_event := csrMod.io.status.wfiEvent 292 293 csrOut.tlb := tlb 294 295 csrOut.debugMode := csrMod.io.status.debugMode 296 297 csrOut.customCtrl match { 298 case custom => 299 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 300 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 301 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 302 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 303 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 304 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 305 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 306 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 307 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 308 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 309 // ICache 310 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 311 // Load violation predictor 312 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 313 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 314 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 315 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 316 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 317 // Branch predictor 318 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 319 // Memory Block 320 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 321 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 322 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 323 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 324 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 325 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 326 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 327 // Rename 328 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 329 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 330 // distribute csr write signal 331 // write to frontend and memory 332 custom.distribute_csr.w.valid := csrWen 333 custom.distribute_csr.w.bits.addr := addr 334 custom.distribute_csr.w.bits.data := wdata 335 // rename single step 336 custom.singlestep := csrMod.io.status.singleStepFlag 337 // trigger 338 custom.frontend_trigger := csrMod.io.status.frontendTrigger 339 custom.mem_trigger := csrMod.io.status.memTrigger 340 // virtual mode 341 custom.virtMode := csrMod.io.status.privState.V.asBool 342 } 343 344 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 345 346 csrToDecode := csrMod.io.toDecode 347} 348 349class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 350 val hartId = Input(UInt(8.W)) 351 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 352 val clintTime = Input(ValidIO(UInt(64.W))) 353 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 354} 355 356class CSRToDecode(implicit p: Parameters) extends XSBundle { 357 val illegalInst = new Bundle { 358 /** 359 * illegal sfence.vma, sinval.vma 360 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 361 */ 362 val sfenceVMA = Bool() 363 364 /** 365 * illegal sfence.w.inval sfence.inval.ir 366 * raise EX_II when isModeHU 367 */ 368 val sfencePart = Bool() 369 370 /** 371 * illegal hfence.gvma, hinval.gvma 372 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 373 * the condition is the same as sfenceVMA 374 */ 375 val hfenceGVMA = Bool() 376 377 /** 378 * illegal hfence.vvma, hinval.vvma 379 * raise EX_II when isModeHU 380 */ 381 val hfenceVVMA = Bool() 382 383 /** 384 * illegal hlv, hlvx, and hsv 385 * raise EX_II when isModeHU && hstatus.HU=0 386 */ 387 val hlsv = Bool() 388 389 /** 390 * decode all fp inst or all vecfp inst 391 * raise EX_II when FS=Off 392 */ 393 val fsIsOff = Bool() 394 395 /** 396 * decode all vec inst 397 * raise EX_II when VS=Off 398 */ 399 val vsIsOff = Bool() 400 401 /** 402 * illegal wfi 403 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 404 */ 405 val wfi = Bool() 406 407 /** 408 * frm reserved 409 * raise EX_II when frm.data > 4 410 */ 411 val frm = Bool() 412 } 413 val virtualInst = new Bundle { 414 /** 415 * illegal sfence.vma, svinval.vma 416 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 417 */ 418 val sfenceVMA = Bool() 419 420 /** 421 * illegal sfence.w.inval sfence.inval.ir 422 * raise EX_VI when isModeVU 423 */ 424 val sfencePart = Bool() 425 426 /** 427 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 428 * raise EX_VI when isModeVS || isModeVU 429 */ 430 val hfence = Bool() 431 432 /** 433 * illegal hlv, hlvx, and hsv 434 * raise EX_VI when isModeVS || isModeVU 435 */ 436 val hlsv = Bool() 437 438 /** 439 * illegal wfi 440 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 441 */ 442 val wfi = Bool() 443 } 444}