1package xiangshan.backend.fu.vector 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.DataHoldBypass 7import xiangshan.backend.fu.vector.Bundles.VConfig 8import xiangshan.backend.fu.vector.utils.ScalaDupToVector 9import xiangshan.backend.fu.{FuConfig, FuncUnit} 10import yunsuan.VialuFixType 11 12class VecNonPipedFuncUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 13 with VecFuncUnitAlias 14{ 15 private val extedVs1 = Wire(UInt(VLEN.W)) 16 17 // modules 18 private val scalaDupToVector = Module(new ScalaDupToVector(VLEN)) 19 20 scalaDupToVector.io.in.scalaData := inData.src(0) 21 scalaDupToVector.io.in.vsew := vsew 22 extedVs1 := scalaDupToVector.io.out.vecData 23 24 private val src0 = Mux(vecCtrl.needScalaSrc, extedVs1, inData.src(0)) // vs1, rs1, fs1, imm 25 private val src1 = WireInit(inData.src(1)) // vs2 only 26 27 protected val vs2 = Mux(isReverse, src0, src1) 28 protected val vs1 = Mux(isReverse, src1, src0) 29 protected val oldVd = inData.src(2) 30 31 protected val outCtrl = DataHoldBypass(io.in.bits.ctrl, io.in.fire) 32 protected val outData = DataHoldBypass(io.in.bits.data, io.in.fire) 33 34 protected val outVecCtrl = outCtrl.vpu.get 35 protected val outVm = outVecCtrl.vm 36 37 // vadc.vv, vsbc.vv need this 38 protected val outNeedClearMask: Bool = VialuFixType.needClearMask(outCtrl.fuOpType) 39 40 protected val outVConfig = if(!cfg.vconfigWakeUp) outCtrl.vpu.get.vconfig else outData.getSrcVConfig.asTypeOf(new VConfig) 41 protected val outVl = outVConfig.vl 42 protected val outOldVd = outData.src(2) 43 // There is no difference between control-dependency or data-dependency for function unit, 44 // but spliting these in ctrl or data bundles is easy to coding. 45 protected val outSrcMask: UInt = if (!cfg.maskWakeUp) outCtrl.vpu.get.vmask else { 46 MuxCase( 47 outData.getSrcMask, Seq( 48 outNeedClearMask -> allMaskFalse, 49 outVm -> allMaskTrue 50 ) 51 ) 52 } 53 54 connectNonPipedCtrlSingal 55} 56