1package xiangshan.backend.fu.vector 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.DataHoldBypass 7import xiangshan.backend.fu.vector.Bundles.VConfig 8import xiangshan.backend.fu.vector.utils.ScalaDupToVector 9import xiangshan.backend.fu.{FuConfig, FuncUnit} 10import xiangshan.ExceptionNO.illegalInstr 11import yunsuan.VialuFixType 12 13class VecNonPipedFuncUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 14 with VecFuncUnitAlias 15{ 16 private val extedVs1 = Wire(UInt(VLEN.W)) 17 18 // modules 19 private val scalaDupToVector = Module(new ScalaDupToVector(VLEN)) 20 21 scalaDupToVector.io.in.scalaData := inData.src(0) 22 scalaDupToVector.io.in.vsew := vsew 23 extedVs1 := scalaDupToVector.io.out.vecData 24 25 private val src0 = Mux(vecCtrl.needScalaSrc, extedVs1, inData.src(0)) // vs1, rs1, fs1, imm 26 private val src1 = WireInit(inData.src(1)) // vs2 only 27 28 protected val vs2 = Mux(isReverse, src0, src1) 29 protected val vs1 = Mux(isReverse, src1, src0) 30 protected val oldVd = inData.src(2) 31 32 protected val outCtrl = DataHoldBypass(io.in.bits.ctrl, io.in.fire) 33 protected val outData = DataHoldBypass(io.in.bits.data, io.in.fire) 34 35 protected val outVecCtrl = outCtrl.vpu.get 36 protected val outVm = outVecCtrl.vm 37 38 // vadc.vv, vsbc.vv need this 39 protected val outNeedClearMask: Bool = VialuFixType.needClearMask(outCtrl.fuOpType) 40 41 protected val outVConfig = if(!cfg.vconfigWakeUp) outCtrl.vpu.get.vconfig else outData.getSrcVConfig.asTypeOf(new VConfig) 42 protected val outVl = outVConfig.vl 43 protected val outOldVd = outData.src(2) 44 // There is no difference between control-dependency or data-dependency for function unit, 45 // but spliting these in ctrl or data bundles is easy to coding. 46 protected val outSrcMask: UInt = if (!cfg.maskWakeUp) outCtrl.vpu.get.vmask else { 47 MuxCase( 48 outData.getSrcMask, Seq( 49 outNeedClearMask -> allMaskFalse, 50 outVm -> allMaskTrue 51 ) 52 ) 53 } 54 55 // vstart illegal 56 if (cfg.exceptionOut.nonEmpty) { 57 val outVstart = outCtrl.vpu.get.vstart 58 val vstartIllegal = outVstart =/= 0.U 59 io.out.bits.ctrl.exceptionVec.get := 0.U.asTypeOf(io.out.bits.ctrl.exceptionVec.get) 60 io.out.bits.ctrl.exceptionVec.get(illegalInstr) := vstartIllegal 61 } 62 63 connectNonPipedCtrlSingal 64} 65