1/**************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 **************************************************************************************** 16 */ 17 18 19package xiangshan.backend.fu.vector 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3._ 23import utils._ 24import yunsuan.VpermType 25import xiangshan.{XSCoreParamsKey, FuType} 26import yunsuan.vector.perm.Permutation 27import yunsuan.vector.{FToSModule, Vfslide1upModule} 28 29class VPPUWrapper(implicit p: Parameters) extends VPUDataModule { 30 31 needReverse := false.B 32 needClearMask := false.B 33 34 // connect f2s 35 val f2s = Module(new FToSModule()) 36 val vfslide1up= Module(new Vfslide1upModule()) 37 38 f2s.io.in.valid := io.in.valid 39 f2s.io.in.src0 := vs1 40 f2s.io.in.src1 := io.in.bits.src(2) 41 f2s.io.in.vstart := 0.U(32.W) // TODO: when vstart >0 , how to solve the problem 42 f2s.io.in.vl := in.uop.ctrl.vconfig.vl 43 f2s.io.in.vsew := in.uop.ctrl.vconfig.vtype.vsew 44 f2s.io.in.vta := in.uop.ctrl.vconfig.vtype.vta 45 f2s.io.in.vma := in.uop.ctrl.vconfig.vtype.vma 46 f2s.io.in.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 47 f2s.io.in.v0 := in.src(3) 48 49 vfslide1up.io.in.valid := io.in.valid 50 vfslide1up.io.in.src0 := vs1 51 vfslide1up.io.in.src1 := vs2 52 vfslide1up.io.in.vstart := 0.U(32.W) // TODO: when vstart >0 , how to solve the problem 53 vfslide1up.io.in.vl := in.uop.ctrl.vconfig.vl 54 vfslide1up.io.in.vsew := in.uop.ctrl.vconfig.vtype.vsew 55 vfslide1up.io.in.vta := in.uop.ctrl.vconfig.vtype.vta 56 vfslide1up.io.in.vma := in.uop.ctrl.vconfig.vtype.vma 57 vfslide1up.io.in.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 58 vfslide1up.io.in.v0 := in.src(3) 59 60 io.out.bits.data := RegNext(Mux(in.uop.ctrl.fuOpType === VpermType.vfmv_s_f, f2s.io.out.vd, 61 Mux(in.uop.ctrl.fuOpType === VpermType.vfslide1up, vfslide1up.io.out.vd, 0.U))) 62 vxsat := 0.U 63 io.out.valid := RegNext(io.in.valid) 64} 65 66class VPermWrapper(implicit p: Parameters) extends VPUDataModule { 67 68 needReverse := false.B 69 needClearMask := false.B 70 71 // connect VPerm 72 val VPerm = Module(new Permutation) 73 VPerm.io.in.bits.opcode := VpermType.getOpcode(in.uop.ctrl.fuOpType).asTypeOf(VPerm.io.in.bits.opcode.cloneType) 74 VPerm.io.in.bits.info.vm := in.uop.ctrl.vm 75 VPerm.io.in.bits.info.ma := in.uop.ctrl.vconfig.vtype.vma 76 VPerm.io.in.bits.info.ta := in.uop.ctrl.vconfig.vtype.vta 77 VPerm.io.in.bits.info.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 78 VPerm.io.in.bits.info.vl := in.uop.ctrl.vconfig.vl 79 80 VPerm.io.in.bits.info.vstart := vstart 81 VPerm.io.in.bits.info.uopIdx := in.uop.ctrl.uopIdx 82 83 VPerm.io.in.bits.info.vxrm := vxrm 84 val srcVdType = Wire(new Bundle{ 85 val srcType2 = UInt(4.W) 86 val srcType1 = UInt(4.W) 87 val vdType = UInt(4.W) 88 }) 89 srcVdType := VpermType.getSrcVdType(in.uop.ctrl.fuOpType, in.uop.ctrl.vconfig.vtype.vsew(1,0)).asTypeOf(srcVdType.cloneType) 90 VPerm.io.in.bits.srcType(0) := srcVdType.srcType2 91 VPerm.io.in.bits.srcType(1) := srcVdType.srcType1 92 VPerm.io.in.bits.vdType := srcVdType.vdType 93 VPerm.io.in.bits.vs1 := vs1 94 VPerm.io.in.bits.vs2 := vs2 95 VPerm.io.in.bits.old_vd := in.src(2) 96 VPerm.io.in.bits.mask := in.src(3) 97 VPerm.io.in.valid := io.in.valid 98 99 // connect io 100 io.out.bits.data := VPerm.io.out.vd 101 vxsat := VPerm.io.out.vxsat 102 io.out.valid := RegNext(io.in.valid) 103} 104 105class VPerm(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN) { 106 XSError(io.in.valid && io.in.bits.uop.ctrl.fuOpType === VpermType.dummy, "VpermType OpType not supported") 107 override val dataModule = Seq( 108 Module(new VPPUWrapper), 109 Module(new VPermWrapper) 110 ) 111 val select0 = io.in.bits.uop.ctrl.fuOpType === VpermType.vfmv_s_f || io.in.bits.uop.ctrl.fuOpType === VpermType.vfslide1up 112 override val select = Seq( 113 io.in.bits.uop.ctrl.fuType === FuType.vppu && select0, 114 io.in.bits.uop.ctrl.fuType === FuType.vppu && !select0 115 ) 116 connectDataModule 117} 118