1///**************************************************************************************** 2// * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3// * Copyright (c) 2020-2021 Peng Cheng Laboratory 4// * 5// * XiangShan is licensed under Mulan PSL v2. 6// * You can use this software according to the terms and conditions of the Mulan PSL v2. 7// * You may obtain a copy of Mulan PSL v2 at: 8// * http://license.coscl.org.cn/MulanPSL2 9// * 10// * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11// * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12// * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13// * 14// * See the Mulan PSL v2 for more details. 15// **************************************************************************************** 16// */ 17// 18// 19//package xiangshan.backend.fu.vector 20// 21//import org.chipsalliance.cde.config.Parameters 22//import chisel3._ 23//import chisel3.util.log2Up 24//import utils._ 25//import yunsuan.VpermType 26//import xiangshan.{FuType, SrcType, XSCoreParamsKey} 27//import yunsuan.vector.perm.Permutation 28//import yunsuan.vector.{FToSModule, Vfslide1upModule} 29//import chisel3.dontTouch 30// 31//class VPPUWrapper(implicit p: Parameters) extends VPUDataModule { 32// 33// needReverse := false.B 34// needClearMask := false.B 35// 36// // connect f2s 37// val f2s = Module(new FToSModule()) 38// val vfslide1up= Module(new Vfslide1upModule()) 39// 40// f2s.io.in.valid := io.in.valid 41// f2s.io.in.src0 := vs1 42// f2s.io.in.src1 := io.in.bits.src(2) 43// f2s.io.in.vstart := 0.U(32.W) // TODO: when vstart >0 , how to solve the problem 44// f2s.io.in.vl := in.uop.ctrl.vconfig.vl 45// f2s.io.in.vsew := in.uop.ctrl.vconfig.vtype.vsew 46// f2s.io.in.vta := in.uop.ctrl.vconfig.vtype.vta 47// f2s.io.in.vma := in.uop.ctrl.vconfig.vtype.vma 48// f2s.io.in.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 49// f2s.io.in.v0 := mask 50// 51// vfslide1up.io.in.valid := io.in.valid 52// vfslide1up.io.in.src0 := vs1 53// vfslide1up.io.in.src1 := vs2 54// vfslide1up.io.in.vstart := 0.U(32.W) // TODO: when vstart >0 , how to solve the problem 55// vfslide1up.io.in.vl := in.uop.ctrl.vconfig.vl 56// vfslide1up.io.in.vsew := in.uop.ctrl.vconfig.vtype.vsew 57// vfslide1up.io.in.vta := in.uop.ctrl.vconfig.vtype.vta 58// vfslide1up.io.in.vma := in.uop.ctrl.vconfig.vtype.vma 59// vfslide1up.io.in.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 60// vfslide1up.io.in.v0 := mask 61// 62// io.out.bits.data := RegNext(Mux(in.uop.ctrl.fuOpType === VpermType.vfmv_s_f, f2s.io.out.vd, 63// Mux(in.uop.ctrl.fuOpType === VpermType.vfslide1up, vfslide1up.io.out.vd, 0.U))) 64// vxsat := 0.U 65// io.out.valid := RegNext(io.in.valid) 66//} 67// 68//class VPermWrapper(implicit p: Parameters) extends VPUDataModule { 69// 70// needReverse := false.B 71// needClearMask := (VpermType.vcompress === in.uop.ctrl.fuOpType) && (in.uop.ctrl.uopIdx(log2Up(MaxUopSize)-1,1) === 0.U) 72// 73// // connect VPerm 74// val VPerm = Module(new Permutation) 75// VPerm.io.in.bits.opcode := VpermType.getOpcode(in.uop.ctrl.fuOpType).asTypeOf(VPerm.io.in.bits.opcode.cloneType) 76// VPerm.io.in.bits.info.vm := in.uop.ctrl.vm 77// VPerm.io.in.bits.info.ma := in.uop.ctrl.vconfig.vtype.vma 78// VPerm.io.in.bits.info.ta := in.uop.ctrl.vconfig.vtype.vta 79// VPerm.io.in.bits.info.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 80// VPerm.io.in.bits.info.vl := in.uop.ctrl.vconfig.vl 81// 82// VPerm.io.in.bits.info.vstart := vstart 83// VPerm.io.in.bits.info.uopIdx := in.uop.ctrl.uopIdx 84// 85// VPerm.io.in.bits.info.vxrm := vxrm 86// val srcVdType = Wire(new Bundle{ 87// val srcType2 = UInt(4.W) 88// val srcType1 = UInt(4.W) 89// val vdType = UInt(4.W) 90// }) 91// srcVdType := VpermType.getSrcVdType(in.uop.ctrl.fuOpType, in.uop.ctrl.vconfig.vtype.vsew(1,0)).asTypeOf(srcVdType.cloneType) 92// VPerm.io.in.bits.srcType(0) := srcVdType.srcType2 93// src1Sew := srcVdType.srcType1(1,0) 94// src1NeedSew := !VpermType.notNeedSew(in.uop.ctrl.fuOpType) 95// VPerm.io.in.bits.srcType(1) := srcVdType.srcType1 96// VPerm.io.in.bits.vdType := srcVdType.vdType 97// // dirty code for VSLIDEUP_VX/VSLIDEDOWN_VX 98// VPerm.io.in.bits.vs1 := vs1 99// VPerm.io.in.bits.vs2 := vs2 100// VPerm.io.in.bits.old_vd := in.src(2) 101// VPerm.io.in.bits.mask := mask 102// VPerm.io.in.valid := io.in.valid 103// 104// // connect io 105// io.out.bits.data := VPerm.io.out.vd 106// vxsat := VPerm.io.out.vxsat 107// io.out.valid := RegNext(io.in.valid) 108//} 109// 110//class VPerm(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN) { 111// XSError(io.in.valid && io.in.bits.uop.ctrl.fuOpType === VpermType.dummy, "VpermType OpType not supported") 112// override val dataModule = Seq( 113// Module(new VPPUWrapper), 114// Module(new VPermWrapper) 115// ) 116// val select0 = io.in.bits.uop.ctrl.fuOpType === VpermType.vfmv_s_f 117// override val select = Seq( 118// io.in.bits.uop.ctrl.fuType === FuType.vppu && select0, 119// io.in.bits.uop.ctrl.fuType === FuType.vppu && !select0 120// ) 121// connectDataModule 122//} 123