1/**************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 **************************************************************************************** 16 */ 17 18 19package xiangshan.backend.fu.vector 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3.{Mux, _} 23import chisel3.util._ 24import utils._ 25import utility._ 26import yunsuan.vector.{VectorFloatAdder,VectorFloatFMA,VectorFloatDivider} 27import yunsuan.VfpuType 28import xiangshan.{FuOpType, SrcType, XSBundle, XSCoreParamsKey, XSModule} 29import xiangshan.backend.fu.fpu.FPUSubModule 30 31class VFPU(implicit p: Parameters) extends FPUSubModule(p(XSCoreParamsKey).VLEN){ 32 XSError(io.in.valid && io.in.bits.uop.ctrl.fuOpType === VfpuType.dummy, "VFPU OpType not supported") 33 XSError(io.in.valid && (io.in.bits.uop.ctrl.vconfig.vtype.vsew === 0.U), "8 bits not supported in VFPU") 34 override val dataModule = null // Only use IO, not dataModule 35 36// rename signal 37 val in = io.in.bits 38 val ctrl = io.in.bits.uop.ctrl 39 val vtype = ctrl.vconfig.vtype 40 val src1Type = io.in.bits.uop.ctrl.srcType 41 42// def some signal 43 val fflagsReg = RegInit(0.U(5.W)) 44 val fflagsWire = WireInit(0.U(5.W)) 45 val dataReg = Reg(io.out.bits.data.cloneType) 46 val dataWire = Wire(dataReg.cloneType) 47 val s_idle :: s_compute :: s_finish :: Nil = Enum(3) 48 val state = RegInit(s_idle) 49 val vfalu = Module(new VfaluWrapper()(p)) 50 val vfmacc = Module(new VfmaccWrapper()(p)) 51 val vfdiv = Module(new VfdivWrapper()(p)) 52 val outValid = vfalu.io.out.valid || vfmacc.io.out.valid || vfdiv.io.out.valid 53 val outFire = vfalu.io.out.fire() || vfmacc.io.out.fire() || vfdiv.io.out.fire() 54 55// reg input signal 56 val s0_uopReg = Reg(io.in.bits.uop.cloneType) 57 val s0_maskReg = Reg(UInt(8.W)) 58 val inHs = io.in.fire() 59 when(inHs && state===s_idle){ 60 s0_uopReg := io.in.bits.uop 61 s0_maskReg := Fill(8, 1.U(1.W)) 62 } 63 64// fsm 65 switch (state) { 66 is (s_idle) { 67 state := Mux(inHs, s_compute, s_idle) 68 } 69 is (s_compute) { 70 state := Mux(outValid, Mux(outFire, s_idle, s_finish), 71 s_compute) 72 } 73 is (s_finish) { 74 state := Mux(io.out.fire(), s_idle, s_finish) 75 } 76 } 77 fflagsReg := Mux(outValid, fflagsWire, fflagsReg) 78 dataReg := Mux(outValid, dataWire, dataReg) 79 80// connect the input port of vfalu 81 vfalu.io.in.bits.src <> in.src 82 vfalu.io.in.bits.srcType <> in.uop.ctrl.srcType 83 vfalu.io.in.bits.round_mode := rm 84 vfalu.io.in.bits.fp_format := vtype.vsew(1,0) 85 vfalu.io.in.bits.opb_widening := false.B // TODO 86 vfalu.io.in.bits.res_widening := false.B // TODO 87 vfalu.io.in.bits.op_code := ctrl.fuOpType 88 vfalu.io.ready_out.s0_mask := s0_maskReg 89 vfalu.io.ready_out.s0_sew := s0_uopReg.ctrl.vconfig.vtype.vsew(1, 0) 90 vfalu.io.ready_out.s0_vl := s0_uopReg.ctrl.vconfig.vl 91 92// connect the input port of vfmacc 93 vfmacc.io.in.bits.src <> in.src 94 vfmacc.io.in.bits.srcType <> in.uop.ctrl.srcType 95 vfmacc.io.in.bits.round_mode := rm 96 vfmacc.io.in.bits.fp_format := vtype.vsew(1, 0) 97 vfmacc.io.in.bits.opb_widening := DontCare // TODO 98 vfmacc.io.in.bits.res_widening := false.B // TODO 99 vfmacc.io.in.bits.op_code := DontCare 100 vfmacc.io.ready_out.s0_mask := s0_maskReg 101 vfmacc.io.ready_out.s0_sew := s0_uopReg.ctrl.vconfig.vtype.vsew(1, 0) 102 vfmacc.io.ready_out.s0_vl := s0_uopReg.ctrl.vconfig.vl 103 104 // connect the input port of vfdiv 105 vfdiv.io.in.bits.src <> in.src 106 vfdiv.io.in.bits.srcType <> in.uop.ctrl.srcType 107 vfdiv.io.in.bits.round_mode := rm 108 vfdiv.io.in.bits.fp_format := vtype.vsew(1, 0) 109 vfdiv.io.in.bits.opb_widening := DontCare // TODO 110 vfdiv.io.in.bits.res_widening := DontCare // TODO 111 vfdiv.io.in.bits.op_code := DontCare 112 vfdiv.io.ready_out.s0_mask := s0_maskReg 113 vfdiv.io.ready_out.s0_sew := s0_uopReg.ctrl.vconfig.vtype.vsew(1, 0) 114 vfdiv.io.ready_out.s0_vl := s0_uopReg.ctrl.vconfig.vl 115 116// connect the output port 117 fflagsWire := LookupTree(s0_uopReg.ctrl.fuOpType, List( 118 VfpuType.fadd -> vfalu.io.out.bits.fflags, 119 VfpuType.fsub -> vfalu.io.out.bits.fflags, 120 VfpuType.fmin -> vfalu.io.out.bits.fflags, 121 VfpuType.fmax -> vfalu.io.out.bits.fflags, 122 VfpuType.fmacc -> vfmacc.io.out.bits.fflags, 123 VfpuType.fdiv -> vfdiv.io.out.bits.fflags, 124 )) 125 fflags := Mux(state === s_compute && outFire, fflagsWire, fflagsReg) 126 dataWire := LookupTree(s0_uopReg.ctrl.fuOpType, List( 127 VfpuType.fadd -> vfalu.io.out.bits.result, 128 VfpuType.fsub -> vfalu.io.out.bits.result, 129 VfpuType.fmin -> vfalu.io.out.bits.result, 130 VfpuType.fmax -> vfalu.io.out.bits.result, 131 VfpuType.fmacc -> vfmacc.io.out.bits.result, 132 VfpuType.fdiv -> vfdiv.io.out.bits.result, 133 )) 134 io.out.bits.data := Mux(state === s_compute && outFire, dataWire, dataReg) 135 io.out.bits.uop := s0_uopReg 136 // valid/ready 137 vfalu.io.in.valid := io.in.valid && VfpuType.isVfalu(in.uop.ctrl.fuOpType) && state === s_idle 138 vfmacc.io.in.valid := io.in.valid && in.uop.ctrl.fuOpType === VfpuType.fmacc && state === s_idle 139 vfdiv.io.in.valid := io.in.valid && in.uop.ctrl.fuOpType === VfpuType.fdiv && state === s_idle 140 io.out.valid := state === s_compute && outValid || state === s_finish 141 vfalu.io.out.ready := io.out.ready 142 vfmacc.io.out.ready := io.out.ready 143 vfdiv.io.out.ready := io.out.ready 144 io.in.ready := state === s_idle 145} 146 147class VFPUWraaperBundle (implicit p: Parameters) extends XSBundle{ 148 val in = Flipped(DecoupledIO(Output(new Bundle { 149 val src = Vec(4, Input(UInt(VLEN.W))) 150 val srcType = Vec(4, SrcType()) 151 152 val round_mode = UInt(3.W) 153 val fp_format = UInt(2.W) // vsew 154 val opb_widening = Bool() 155 val res_widening = Bool() 156 val op_code = FuOpType() 157 }))) 158 159 val ready_out = Input(new Bundle { 160 val s0_mask = UInt((VLEN / 16).W) 161 val s0_sew = UInt(2.W) 162 val s0_vl = UInt(8.W) 163 }) 164 165 val out = DecoupledIO(Output(new Bundle { 166 val result = UInt(128.W) 167 val fflags = UInt(5.W) 168 })) 169} 170 171class VfdivWrapper(implicit p: Parameters) extends XSModule{ 172 val Latency = List(5, 7, 12) 173 val AdderWidth = XLEN 174 val NumAdder = VLEN / XLEN 175 176 val io = IO(new VFPUWraaperBundle) 177 178 val in = io.in.bits 179 val out = io.out.bits 180 val inHs = io.in.fire() 181 182 val s0_mask = io.ready_out.s0_mask 183 val s0_sew = io.ready_out.s0_sew 184 val s0_vl = io.ready_out.s0_vl 185 186 val vfdiv = Seq.fill(NumAdder)(Module(new VectorFloatDivider())) 187 val src1 = Mux(in.srcType(0) === SrcType.vp, in.src(0), VecExtractor(in.fp_format, in.src(0))) 188 val src2 = Mux(in.srcType(1) === SrcType.vp, in.src(1), VecExtractor(in.fp_format, in.src(1))) 189 for (i <- 0 until NumAdder) { 190 vfdiv(i).io.opb_i := Mux(inHs, src1(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 191 vfdiv(i).io.opa_i := Mux(inHs, src2(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 192 vfdiv(i).io.is_vec_i := true.B // If you can enter, it must be vector 193 vfdiv(i).io.rm_i := in.round_mode 194 vfdiv(i).io.fp_format_i := Mux(inHs, in.fp_format, 3.U(2.W)) 195 vfdiv(i).io.start_valid_i := io.in.valid 196 vfdiv(i).io.finish_ready_i := io.out.ready 197 vfdiv(i).io.flush_i := false.B // TODO 198 } 199 200 val s4_fflagsVec = VecInit(vfdiv.map(_.io.fflags_o)).asUInt() 201 val s4_fflags16vl = fflagsGen(s0_mask, s4_fflagsVec, List.range(0, 8)) 202 val s4_fflags32vl = fflagsGen(s0_mask, s4_fflagsVec, List(0, 1, 4, 5)) 203 val s4_fflags64vl = fflagsGen(s0_mask, s4_fflagsVec, List(0, 4)) 204 val s4_fflags = LookupTree(s0_sew(1, 0), List( 205 "b01".U -> Mux(s0_vl.orR, s4_fflags16vl(s0_vl - 1.U), 0.U(5.W)), 206 "b10".U -> Mux(s0_vl.orR, s4_fflags32vl(s0_vl - 1.U), 0.U(5.W)), 207 "b11".U -> Mux(s0_vl.orR, s4_fflags64vl(s0_vl - 1.U), 0.U(5.W)), 208 )) 209 out.fflags := s4_fflags 210 211 val s4_result = VecInit(vfdiv.map(_.io.fpdiv_res_o)).asUInt() 212 out.result := s4_result 213 214 io.in.ready := VecInit(vfdiv.map(_.io.start_ready_o)).asUInt().andR() 215 io.out.valid := VecInit(vfdiv.map(_.io.finish_valid_o)).asUInt().andR() 216} 217 218class VfmaccWrapper(implicit p: Parameters) extends XSModule{ 219 val Latency = 3 220 val AdderWidth = XLEN 221 val NumAdder = VLEN / XLEN 222 223 val io = IO(new VFPUWraaperBundle) 224 225 val in = io.in.bits 226 val out = io.out.bits 227 val inHs = io.in.fire() 228 229 val validPipe = Seq.fill(Latency)(RegInit(false.B)) 230 validPipe.zipWithIndex.foreach { 231 case (valid, idx) => 232 val _valid = if (idx == 0) Mux(inHs, true.B, false.B) else validPipe(idx - 1) 233 valid := _valid 234 } 235 val s0_mask = io.ready_out.s0_mask 236 val s0_sew = io.ready_out.s0_sew 237 val s0_vl = io.ready_out.s0_vl 238 239 val vfmacc = Seq.fill(NumAdder)(Module(new VectorFloatFMA())) 240 val src1 = Mux(in.srcType(0) === SrcType.vp, in.src(0), VecExtractor(in.fp_format, in.src(0))) 241 val src2 = Mux(in.srcType(1) === SrcType.vp, in.src(1), VecExtractor(in.fp_format, in.src(1))) 242 val src3 = Mux(in.srcType(2) === SrcType.vp, in.src(2), VecExtractor(in.fp_format, in.src(2))) 243 for (i <- 0 until NumAdder) { 244 vfmacc(i).io.fp_a := Mux(inHs, src1(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 245 vfmacc(i).io.fp_b := Mux(inHs, src2(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 246 vfmacc(i).io.fp_c := Mux(inHs, src3(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 247 vfmacc(i).io.is_vec := true.B // If you can enter, it must be vector 248 vfmacc(i).io.round_mode := in.round_mode 249 vfmacc(i).io.fp_format := Mux(inHs, in.fp_format, 3.U(2.W)) 250 vfmacc(i).io.res_widening := in.res_widening // TODO 251 } 252 253 // output signal generation 254 val s2_fflagsVec = VecInit(vfmacc.map(_.io.fflags)).asUInt() 255 val s2_fflags16vl = fflagsGen(s0_mask, s2_fflagsVec, List.range(0, 8)) 256 val s2_fflags32vl = fflagsGen(s0_mask, s2_fflagsVec, List(0, 1, 4, 5)) 257 val s2_fflags64vl = fflagsGen(s0_mask, s2_fflagsVec, List(0, 4)) 258 val s2_fflags = LookupTree(s0_sew(1, 0), List( 259 "b01".U -> Mux(s0_vl.orR, s2_fflags16vl(s0_vl - 1.U), 0.U(5.W)), 260 "b10".U -> Mux(s0_vl.orR, s2_fflags32vl(s0_vl - 1.U), 0.U(5.W)), 261 "b11".U -> Mux(s0_vl.orR, s2_fflags64vl(s0_vl - 1.U), 0.U(5.W)), 262 )) 263 out.fflags := s2_fflags 264 265 val s2_result = VecInit(vfmacc.map(_.io.fp_result)).asUInt() 266 out.result := s2_result 267 268 io.in.ready := true.B 269 io.out.valid := validPipe(Latency - 1) 270} 271 272class VfaluWrapper(implicit p: Parameters) extends XSModule{ 273 val Latency = 2 274 val AdderWidth = XLEN 275 val NumAdder = VLEN / XLEN 276 277 val io = IO(new VFPUWraaperBundle) 278 279 val in = io.in.bits 280 val out = io.out.bits 281 val inHs = io.in.fire() 282 283 // reg input signal 284 val validPipe = Seq.fill(Latency)(RegInit(false.B)) 285 validPipe.zipWithIndex.foreach { 286 case (valid, idx) => 287 val _valid = if (idx == 0) Mux(inHs, true.B, false.B) else validPipe(idx - 1) 288 valid := _valid 289 } 290 val s0_mask = io.ready_out.s0_mask 291 val s0_sew = io.ready_out.s0_sew 292 val s0_vl = io.ready_out.s0_vl 293 294 // connect the input signal 295 val vfalu = Seq.fill(NumAdder)(Module(new VectorFloatAdder())) 296 val src1 = Mux(in.srcType(0) === SrcType.vp, in.src(0), VecExtractor(in.fp_format, in.src(0))) 297 val src2 = Mux(in.srcType(1) === SrcType.vp, in.src(1), VecExtractor(in.fp_format, in.src(1))) 298 for (i <- 0 until NumAdder) { 299 vfalu(i).io.fp_b := Mux(inHs, src1(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 300 vfalu(i).io.fp_a := Mux(inHs, src2(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 301 vfalu(i).io.is_vec := true.B // If you can enter, it must be vector 302 vfalu(i).io.round_mode := in.round_mode 303 vfalu(i).io.fp_format := Mux(inHs, in.fp_format, 3.U(2.W)) 304 vfalu(i).io.opb_widening := in.opb_widening // TODO 305 vfalu(i).io.res_widening := in.res_widening // TODO 306 vfalu(i).io.op_code := in.op_code 307 } 308 309 // output signal generation 310 val s0_fflagsVec = VecInit(vfalu.map(_.io.fflags)).asUInt() 311 val s0_fflags16vl = fflagsGen(s0_mask, s0_fflagsVec, List.range(0, 8)) 312 val s0_fflags32vl = fflagsGen(s0_mask, s0_fflagsVec, List(0, 1, 4, 5)) 313 val s0_fflags64vl = fflagsGen(s0_mask, s0_fflagsVec, List(0, 4)) 314 val s0_fflags = LookupTree(s0_sew(1, 0), List( 315 "b01".U -> Mux(s0_vl.orR, s0_fflags16vl(s0_vl - 1.U), 0.U(5.W)), 316 "b10".U -> Mux(s0_vl.orR, s0_fflags32vl(s0_vl - 1.U), 0.U(5.W)), 317 "b11".U -> Mux(s0_vl.orR, s0_fflags64vl(s0_vl - 1.U), 0.U(5.W)), 318 )) 319 val s1_fflags = RegEnable(s0_fflags, validPipe(Latency-2)) 320 out.fflags := s1_fflags 321 322 val s0_result = VecInit(vfalu.map(_.io.fp_result)).asUInt() 323 val s1_result = RegEnable(s0_result, validPipe(Latency-2)) 324 out.result := s1_result 325 326 io.in.ready := true.B 327 io.out.valid := validPipe(Latency-1) 328} 329 330object fflagsGen{ 331 def fflagsGen(vmask: UInt, fflagsResult:UInt, idx:List[Int] = List(0, 1, 4, 5)): Vec[UInt] = { 332 var num = idx.length 333 val fflags = Seq.fill(num)(Wire(UInt(5.W))) 334 fflags.zip(vmask(num-1, 0).asBools().reverse).zip(idx).foreach { 335 case ((fflags0, mask), id) => 336 fflags0 := Mux(mask, fflagsResult(id*5+4,id*5+0), 0.U) 337 } 338 val fflagsVl = Wire(Vec(num,UInt(5.W))) 339 for (i <- 0 until num) { 340 val _fflags = if (i == 0) fflags(i) else (fflagsVl(i - 1) | fflags(i)) 341 fflagsVl(i) := _fflags 342 } 343 fflagsVl 344 } 345 346 def apply(vmask: UInt, fflagsResult:UInt, idx:List[Int] = List(0, 1, 4, 5)): Vec[UInt] = { 347 fflagsGen(vmask, fflagsResult, idx) 348 } 349} 350 351object VecExtractor{ 352 def xf2v_sew(sew: UInt, xf:UInt): UInt = { 353 LookupTree(sew(1, 0), List( 354 "b00".U -> VecInit(Seq.fill(16)(xf(7, 0))).asUInt, 355 "b01".U -> VecInit(Seq.fill(8)(xf(15, 0))).asUInt, 356 "b10".U -> VecInit(Seq.fill(4)(xf(31, 0))).asUInt, 357 "b11".U -> VecInit(Seq.fill(2)(xf(63, 0))).asUInt, 358 )) 359 } 360 361 def apply(sew: UInt, xf: UInt): UInt = { 362 xf2v_sew(sew, xf) 363 } 364}