1/**************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 **************************************************************************************** 16 */ 17 18 19package xiangshan.backend.fu.vector 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3.{Mux, _} 23import chisel3.util._ 24import utils._ 25import utility._ 26import yunsuan.vector.{VectorFloatAdder,VectorFloatFMA,VectorFloatDivider} 27import yunsuan.VfpuType 28import xiangshan.{FuOpType, SrcType, XSBundle, XSCoreParamsKey, XSModule} 29import xiangshan.backend.fu.fpu.FPUSubModule 30 31class VFPU(implicit p: Parameters) extends FPUSubModule(p(XSCoreParamsKey).VLEN){ 32 XSError(io.in.valid && io.in.bits.uop.ctrl.fuOpType === VfpuType.dummy, "VFPU OpType not supported") 33 XSError(io.in.valid && (io.in.bits.uop.ctrl.vconfig.vtype.vsew === 0.U), "8 bits not supported in VFPU") 34 override val dataModule = null // Only use IO, not dataModule 35 36// rename signal 37 val in = io.in.bits 38 val ctrl = io.in.bits.uop.ctrl 39 val vtype = ctrl.vconfig.vtype 40 val src1Type = io.in.bits.uop.ctrl.srcType 41 val uopIdx = ctrl.uopIdx 42 43// def some signal 44 val fflagsReg = RegInit(0.U(5.W)) 45 val fflagsWire = WireInit(0.U(5.W)) 46 val dataReg = Reg(io.out.bits.data.cloneType) 47 val dataWire = Wire(dataReg.cloneType) 48 val s_idle :: s_compute :: s_finish :: Nil = Enum(3) 49 val state = RegInit(s_idle) 50 val vfalu = Module(new VfaluWrapper()(p)) 51 val vfmacc = Module(new VfmaccWrapper()(p)) 52 val vfdiv = Module(new VfdivWrapper()(p)) 53 val outValid = vfalu.io.out.valid || vfmacc.io.out.valid || vfdiv.io.out.valid 54 val outFire = vfalu.io.out.fire() || vfmacc.io.out.fire() || vfdiv.io.out.fire() 55 56// reg input signal 57 val s0_uopReg = Reg(io.in.bits.uop.cloneType) 58 val s0_maskReg = Reg(UInt(8.W)) 59 val inHs = io.in.fire() 60 when(inHs && state===s_idle){ 61 s0_uopReg := io.in.bits.uop 62 s0_maskReg := Fill(8, 1.U(1.W)) 63 } 64 65// fsm 66 switch (state) { 67 is (s_idle) { 68 state := Mux(inHs, s_compute, s_idle) 69 } 70 is (s_compute) { 71 state := Mux(outValid, Mux(outFire, s_idle, s_finish), 72 s_compute) 73 } 74 is (s_finish) { 75 state := Mux(io.out.fire(), s_idle, s_finish) 76 } 77 } 78 fflagsReg := Mux(outValid, fflagsWire, fflagsReg) 79 dataReg := Mux(outValid, dataWire, dataReg) 80 81// connect the input port of vfalu 82 vfalu.io.in.bits.src <> in.src 83 vfalu.io.in.bits.srcType <> in.uop.ctrl.srcType 84 vfalu.io.in.bits.round_mode := rm 85 vfalu.io.in.bits.fp_format := vtype.vsew(1,0) 86 vfalu.io.in.bits.uopIdx := uopIdx(0) //TODO 87 vfalu.io.in.bits.opb_widening := false.B // TODO 88 vfalu.io.in.bits.res_widening := false.B // TODO 89 vfalu.io.in.bits.op_code := ctrl.fuOpType 90 vfalu.io.ready_out.s0_mask := s0_maskReg 91 vfalu.io.ready_out.s0_sew := s0_uopReg.ctrl.vconfig.vtype.vsew(1, 0) 92 vfalu.io.ready_out.s0_vl := s0_uopReg.ctrl.vconfig.vl 93 94// connect the input port of vfmacc 95 vfmacc.io.in.bits.src <> in.src 96 vfmacc.io.in.bits.srcType <> in.uop.ctrl.srcType 97 vfmacc.io.in.bits.round_mode := rm 98 vfmacc.io.in.bits.fp_format := vtype.vsew(1, 0) 99 vfmacc.io.in.bits.uopIdx := uopIdx(0) //TODO 100 vfmacc.io.in.bits.opb_widening := DontCare // TODO 101 vfmacc.io.in.bits.res_widening := false.B // TODO 102 vfmacc.io.in.bits.op_code := DontCare 103 vfmacc.io.ready_out.s0_mask := s0_maskReg 104 vfmacc.io.ready_out.s0_sew := s0_uopReg.ctrl.vconfig.vtype.vsew(1, 0) 105 vfmacc.io.ready_out.s0_vl := s0_uopReg.ctrl.vconfig.vl 106 107 // connect the input port of vfdiv 108 vfdiv.io.in.bits.src <> in.src 109 vfdiv.io.in.bits.srcType <> in.uop.ctrl.srcType 110 vfdiv.io.in.bits.round_mode := rm 111 vfdiv.io.in.bits.fp_format := vtype.vsew(1, 0) 112 vfdiv.io.in.bits.uopIdx := uopIdx(0) // TODO 113 vfdiv.io.in.bits.opb_widening := DontCare // TODO 114 vfdiv.io.in.bits.res_widening := DontCare // TODO 115 vfdiv.io.in.bits.op_code := DontCare 116 vfdiv.io.ready_out.s0_mask := s0_maskReg 117 vfdiv.io.ready_out.s0_sew := s0_uopReg.ctrl.vconfig.vtype.vsew(1, 0) 118 vfdiv.io.ready_out.s0_vl := s0_uopReg.ctrl.vconfig.vl 119 120// connect the output port 121 fflagsWire := LookupTree(s0_uopReg.ctrl.fuOpType, List( 122 VfpuType.fadd -> vfalu.io.out.bits.fflags, 123 VfpuType.fsub -> vfalu.io.out.bits.fflags, 124 VfpuType.fmin -> vfalu.io.out.bits.fflags, 125 VfpuType.fmax -> vfalu.io.out.bits.fflags, 126 VfpuType.fmacc -> vfmacc.io.out.bits.fflags, 127 VfpuType.fdiv -> vfdiv.io.out.bits.fflags, 128 )) 129 fflags := Mux(state === s_compute && outFire, fflagsWire, fflagsReg) 130 dataWire := LookupTree(s0_uopReg.ctrl.fuOpType, List( 131 VfpuType.fadd -> vfalu.io.out.bits.result, 132 VfpuType.fsub -> vfalu.io.out.bits.result, 133 VfpuType.fmin -> vfalu.io.out.bits.result, 134 VfpuType.fmax -> vfalu.io.out.bits.result, 135 VfpuType.fmacc -> vfmacc.io.out.bits.result, 136 VfpuType.fdiv -> vfdiv.io.out.bits.result, 137 )) 138 io.out.bits.data := Mux(state === s_compute && outFire, dataWire, dataReg) 139 io.out.bits.uop := s0_uopReg 140 // valid/ready 141 vfalu.io.in.valid := io.in.valid && VfpuType.isVfalu(in.uop.ctrl.fuOpType) && state === s_idle 142 vfmacc.io.in.valid := io.in.valid && in.uop.ctrl.fuOpType === VfpuType.fmacc && state === s_idle 143 vfdiv.io.in.valid := io.in.valid && in.uop.ctrl.fuOpType === VfpuType.fdiv && state === s_idle 144 io.out.valid := state === s_compute && outValid || state === s_finish 145 vfalu.io.out.ready := io.out.ready 146 vfmacc.io.out.ready := io.out.ready 147 vfdiv.io.out.ready := io.out.ready 148 io.in.ready := state === s_idle 149} 150 151class VFPUWraaperBundle (implicit p: Parameters) extends XSBundle{ 152 val in = Flipped(DecoupledIO(Output(new Bundle { 153 val src = Vec(4, Input(UInt(VLEN.W))) 154 val srcType = Vec(4, SrcType()) 155 156 val round_mode = UInt(3.W) 157 val fp_format = UInt(2.W) // vsew 158 val uopIdx = Bool() 159 val opb_widening = Bool() 160 val res_widening = Bool() 161 val op_code = FuOpType() 162 }))) 163 164 val ready_out = Input(new Bundle { 165 val s0_mask = UInt((VLEN / 16).W) 166 val s0_sew = UInt(2.W) 167 val s0_vl = UInt(8.W) 168 }) 169 170 val out = DecoupledIO(Output(new Bundle { 171 val result = UInt(128.W) 172 val fflags = UInt(5.W) 173 })) 174} 175 176class VfdivWrapper(implicit p: Parameters) extends XSModule{ 177 val Latency = List(5, 7, 12) 178 val AdderWidth = XLEN 179 val NumAdder = VLEN / XLEN 180 181 val io = IO(new VFPUWraaperBundle) 182 183 val in = io.in.bits 184 val out = io.out.bits 185 val inHs = io.in.fire() 186 187 val s0_mask = io.ready_out.s0_mask 188 val s0_sew = io.ready_out.s0_sew 189 val s0_vl = io.ready_out.s0_vl 190 191 val vfdiv = Seq.fill(NumAdder)(Module(new VectorFloatDivider())) 192 val src1 = Mux(in.srcType(0) === SrcType.vp, in.src(0), VecExtractor(in.fp_format, in.src(0))) 193 val src2 = Mux(in.srcType(1) === SrcType.vp, in.src(1), VecExtractor(in.fp_format, in.src(1))) 194 for (i <- 0 until NumAdder) { 195 vfdiv(i).io.opb_i := Mux(inHs, src1(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 196 vfdiv(i).io.opa_i := Mux(inHs, src2(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 197 vfdiv(i).io.is_vec_i := true.B // If you can enter, it must be vector 198 vfdiv(i).io.rm_i := in.round_mode 199 vfdiv(i).io.fp_format_i := Mux(inHs, in.fp_format, 3.U(2.W)) 200 vfdiv(i).io.start_valid_i := io.in.valid 201 vfdiv(i).io.finish_ready_i := io.out.ready 202 vfdiv(i).io.flush_i := false.B // TODO 203 } 204 205 val s4_fflagsVec = VecInit(vfdiv.map(_.io.fflags_o)).asUInt() 206 val s4_fflags16vl = fflagsGen(s0_mask, s4_fflagsVec, List.range(0, 8)) 207 val s4_fflags32vl = fflagsGen(s0_mask, s4_fflagsVec, List(0, 1, 4, 5)) 208 val s4_fflags64vl = fflagsGen(s0_mask, s4_fflagsVec, List(0, 4)) 209 val s4_fflags = LookupTree(s0_sew(1, 0), List( 210 "b01".U -> Mux(s0_vl.orR, s4_fflags16vl(s0_vl - 1.U), 0.U(5.W)), 211 "b10".U -> Mux(s0_vl.orR, s4_fflags32vl(s0_vl - 1.U), 0.U(5.W)), 212 "b11".U -> Mux(s0_vl.orR, s4_fflags64vl(s0_vl - 1.U), 0.U(5.W)), 213 )) 214 out.fflags := s4_fflags 215 216 val s4_result = VecInit(vfdiv.map(_.io.fpdiv_res_o)).asUInt() 217 out.result := s4_result 218 219 io.in.ready := VecInit(vfdiv.map(_.io.start_ready_o)).asUInt().andR() 220 io.out.valid := VecInit(vfdiv.map(_.io.finish_valid_o)).asUInt().andR() 221} 222 223class VfmaccWrapper(implicit p: Parameters) extends XSModule{ 224 val Latency = 3 225 val AdderWidth = XLEN 226 val NumAdder = VLEN / XLEN 227 228 val io = IO(new VFPUWraaperBundle) 229 230 val in = io.in.bits 231 val out = io.out.bits 232 val inHs = io.in.fire() 233 234 val validPipe = Seq.fill(Latency)(RegInit(false.B)) 235 validPipe.zipWithIndex.foreach { 236 case (valid, idx) => 237 val _valid = if (idx == 0) Mux(inHs, true.B, false.B) else validPipe(idx - 1) 238 valid := _valid 239 } 240 val s0_mask = io.ready_out.s0_mask 241 val s0_sew = io.ready_out.s0_sew 242 val s0_vl = io.ready_out.s0_vl 243 244 val vfmacc = Seq.fill(NumAdder)(Module(new VectorFloatFMA())) 245 val src1 = Mux(in.srcType(0) === SrcType.vp, in.src(0), VecExtractor(in.fp_format, in.src(0))) 246 val src2 = Mux(in.srcType(1) === SrcType.vp, in.src(1), VecExtractor(in.fp_format, in.src(1))) 247 val src3 = Mux(in.srcType(2) === SrcType.vp, in.src(2), VecExtractor(in.fp_format, in.src(2))) 248 for (i <- 0 until NumAdder) { 249 vfmacc(i).io.fp_a := Mux(inHs, src1(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 250 vfmacc(i).io.fp_b := Mux(inHs, src2(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 251 vfmacc(i).io.fp_c := Mux(inHs, src3(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 252 vfmacc(i).io.uop_idx := in.uopIdx 253 vfmacc(i).io.widen_a := 0.U // TODO : 254 vfmacc(i).io.widen_b := 0.U // TODO : 255 vfmacc(i).io.frs1 := in.src(2)(63,0) 256 vfmacc(i).io.is_frs1 := false.B // TODO: support vf inst 257 vfmacc(i).io.op_code := in.op_code 258 vfmacc(i).io.is_vec := true.B // If you can enter, it must be vector 259 vfmacc(i).io.round_mode := in.round_mode 260 vfmacc(i).io.fp_format := Mux(inHs, in.fp_format, 3.U(2.W)) 261 vfmacc(i).io.res_widening := in.res_widening // TODO 262 } 263 264 // output signal generation 265 val s2_fflagsVec = VecInit(vfmacc.map(_.io.fflags)).asUInt() 266 val s2_fflags16vl = fflagsGen(s0_mask, s2_fflagsVec, List.range(0, 8)) 267 val s2_fflags32vl = fflagsGen(s0_mask, s2_fflagsVec, List(0, 1, 4, 5)) 268 val s2_fflags64vl = fflagsGen(s0_mask, s2_fflagsVec, List(0, 4)) 269 val s2_fflags = LookupTree(s0_sew(1, 0), List( 270 "b01".U -> Mux(s0_vl.orR, s2_fflags16vl(s0_vl - 1.U), 0.U(5.W)), 271 "b10".U -> Mux(s0_vl.orR, s2_fflags32vl(s0_vl - 1.U), 0.U(5.W)), 272 "b11".U -> Mux(s0_vl.orR, s2_fflags64vl(s0_vl - 1.U), 0.U(5.W)), 273 )) 274 out.fflags := s2_fflags 275 276 val s2_result = VecInit(vfmacc.map(_.io.fp_result)).asUInt() 277 out.result := s2_result 278 279 io.in.ready := true.B 280 io.out.valid := validPipe(Latency - 1) 281} 282 283class VfaluWrapper(implicit p: Parameters) extends XSModule{ 284 val Latency = 2 285 val AdderWidth = XLEN 286 val NumAdder = VLEN / XLEN 287 288 val io = IO(new VFPUWraaperBundle) 289 290 val in = io.in.bits 291 val out = io.out.bits 292 val inHs = io.in.fire() 293 294 // reg input signal 295 val validPipe = Seq.fill(Latency)(RegInit(false.B)) 296 validPipe.zipWithIndex.foreach { 297 case (valid, idx) => 298 val _valid = if (idx == 0) Mux(inHs, true.B, false.B) else validPipe(idx - 1) 299 valid := _valid 300 } 301 val s0_mask = io.ready_out.s0_mask 302 val s0_sew = io.ready_out.s0_sew 303 val s0_vl = io.ready_out.s0_vl 304 305 // connect the input signal 306 val vfalu = Seq.fill(NumAdder)(Module(new VectorFloatAdder())) 307 val src1 = Mux(in.srcType(0) === SrcType.vp, in.src(0), VecExtractor(in.fp_format, in.src(0))) 308 val src2 = Mux(in.srcType(1) === SrcType.vp, in.src(1), VecExtractor(in.fp_format, in.src(1))) 309 for (i <- 0 until NumAdder) { 310 vfalu(i).io.fp_b := Mux(inHs, src1(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 311 vfalu(i).io.fp_a := Mux(inHs, src2(AdderWidth * (i + 1) - 1, AdderWidth * i), 0.U) 312 vfalu(i).io.widen_b := Mux(inHs, Cat(src1((AdderWidth / 2) * (i + 3) - 1, (AdderWidth / 2) * (i + 2)), src1((AdderWidth / 2) * (i + 1) - 1, (AdderWidth / 2) * i)), 0.U) 313 vfalu(i).io.widen_a := Mux(inHs, Cat(src2((AdderWidth / 2) * (i + 3) - 1, (AdderWidth / 2) * (i + 2)), src2((AdderWidth / 2) * (i + 1) - 1, (AdderWidth / 2) * i)), 0.U) 314 vfalu(i).io.frs1 := in.src(2)(63, 0) 315 vfalu(i).io.is_frs1 := false.B // TODO: support vf inst 316 vfalu(i).io.mask := 0.U //TODO 317 vfalu(i).io.uop_idx := in.uopIdx //TODO 318 vfalu(i).io.is_vec := true.B // If you can enter, it must be vector 319 vfalu(i).io.round_mode := in.round_mode 320 vfalu(i).io.fp_format := Mux(inHs, in.fp_format, 3.U(2.W)) 321 vfalu(i).io.opb_widening := in.opb_widening // TODO 322 vfalu(i).io.res_widening := in.res_widening // TODO 323 vfalu(i).io.op_code := in.op_code 324 } 325 326 // output signal generation 327 val s0_fflagsVec = VecInit(vfalu.map(_.io.fflags)).asUInt() 328 val s0_fflags16vl = fflagsGen(s0_mask, s0_fflagsVec, List.range(0, 8)) 329 val s0_fflags32vl = fflagsGen(s0_mask, s0_fflagsVec, List(0, 1, 4, 5)) 330 val s0_fflags64vl = fflagsGen(s0_mask, s0_fflagsVec, List(0, 4)) 331 val s0_fflags = LookupTree(s0_sew(1, 0), List( 332 "b01".U -> Mux(s0_vl.orR, s0_fflags16vl(s0_vl - 1.U), 0.U(5.W)), 333 "b10".U -> Mux(s0_vl.orR, s0_fflags32vl(s0_vl - 1.U), 0.U(5.W)), 334 "b11".U -> Mux(s0_vl.orR, s0_fflags64vl(s0_vl - 1.U), 0.U(5.W)), 335 )) 336 val s1_fflags = RegEnable(s0_fflags, validPipe(Latency-2)) 337 out.fflags := s1_fflags 338 339 val s0_result = VecInit(vfalu.map(_.io.fp_result)).asUInt() 340 val s1_result = RegEnable(s0_result, validPipe(Latency-2)) 341 out.result := s1_result 342 343 io.in.ready := true.B 344 io.out.valid := validPipe(Latency-1) 345} 346 347object fflagsGen{ 348 def fflagsGen(vmask: UInt, fflagsResult:UInt, idx:List[Int] = List(0, 1, 4, 5)): Vec[UInt] = { 349 var num = idx.length 350 val fflags = Seq.fill(num)(Wire(UInt(5.W))) 351 fflags.zip(vmask(num-1, 0).asBools().reverse).zip(idx).foreach { 352 case ((fflags0, mask), id) => 353 fflags0 := Mux(mask, fflagsResult(id*5+4,id*5+0), 0.U) 354 } 355 val fflagsVl = Wire(Vec(num,UInt(5.W))) 356 for (i <- 0 until num) { 357 val _fflags = if (i == 0) fflags(i) else (fflagsVl(i - 1) | fflags(i)) 358 fflagsVl(i) := _fflags 359 } 360 fflagsVl 361 } 362 363 def apply(vmask: UInt, fflagsResult:UInt, idx:List[Int] = List(0, 1, 4, 5)): Vec[UInt] = { 364 fflagsGen(vmask, fflagsResult, idx) 365 } 366} 367 368object VecExtractor{ 369 def xf2v_sew(sew: UInt, xf:UInt): UInt = { 370 LookupTree(sew(1, 0), List( 371 "b00".U -> VecInit(Seq.fill(16)(xf(7, 0))).asUInt, 372 "b01".U -> VecInit(Seq.fill(8)(xf(15, 0))).asUInt, 373 "b10".U -> VecInit(Seq.fill(4)(xf(31, 0))).asUInt, 374 "b11".U -> VecInit(Seq.fill(2)(xf(63, 0))).asUInt, 375 )) 376 } 377 378 def apply(sew: UInt, xf: UInt): UInt = { 379 xf2v_sew(sew, xf) 380 } 381}