xref: /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgtu.scala (revision 83ba63b34cf09b33c0a9e1b3203138e51af4491b) 
1/****************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 *          http://license.coscl.org.cn/MulanPSL2
9 *
10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13 *
14 * See the Mulan PSL v2 for more details.
15 ****************************************************************************************
16 */
17
18
19package xiangshan.backend.fu.vector
20
21import org.chipsalliance.cde.config.Parameters
22import chisel3._
23import chisel3.util._
24import chiseltest._
25import org.scalatest.flatspec.AnyFlatSpec
26import org.scalatest.matchers.must.Matchers
27import top.{ArgParser, BaseConfig, DefaultConfig}
28import xiangshan._
29import xiangshan.backend.fu.vector.Bundles.{Vl}
30import yunsuan.vector._
31
32class Mgtu(vlen: Int)(implicit p: Parameters) extends  Module {
33  val io = IO(new MgtuIO(vlen))
34
35  val in = io.in
36  val vd = in.vd
37  val vl = in.vl
38
39  /**
40    * Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of vta
41    * 1. 1.U(vlen.W) << vl get a bit 1 followed by vl bits 0 (100...000)
42    * 2. 1.U(vlen.W) << vl - 1.U(vlen.W) get a bits with vl bits 1 (11...111)
43    * 3. ~((1.U(vlen.W) << vl) - 1.U(vlen.W)) get a bits with (vlen - vl) bits 1 followed by vl bits 0 (11...1100...000)
44    * 4. vd | tailBit set the high (vlen - vl) bits of vd to 1 (11...11xx...xx)
45    */
46  private val tailBit = ~((1.U(vlen.W) << vl) - 1.U(vlen.W))
47
48  io.out.vd := vd | tailBit
49}
50
51
52class MgtuIO(vlen: Int)(implicit p: Parameters) extends Bundle {
53  val in = new Bundle {
54    val vd = Input(UInt(vlen.W))
55    val vl = Input(Vl())
56  }
57  val out = new Bundle {
58    val vd = Output(UInt(vlen.W))
59  }
60}
61