1/**************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 **************************************************************************************** 16 */ 17 18 19package xiangshan.backend.fu.vector 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import chiseltest._ 25import org.scalatest.flatspec.AnyFlatSpec 26import org.scalatest.matchers.must.Matchers 27import top.{ArgParser, BaseConfig, DefaultConfig} 28import xiangshan._ 29import xiangshan.backend.fu.vector.Bundles.{Vl} 30import yunsuan.vector._ 31 32class Mgtu(vlen: Int)(implicit p: Parameters) extends Module { 33 val io = IO(new MgtuIO(vlen)) 34 35 val in = io.in 36 val vd = in.vd 37 val vl = in.vl 38 39 /* 40 * Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of vta 41 */ 42 private val vdWithTail = Wire(Vec(vlen, UInt(1.W))) 43 vdWithTail.zipWithIndex.foreach{ case (bit, idx) => 44 bit := Mux(idx.U < vl, vd(idx), 1.U) 45 } 46 47 io.out.vd := vdWithTail.asUInt 48} 49 50 51class MgtuIO(vlen: Int)(implicit p: Parameters) extends Bundle { 52 val in = new Bundle { 53 val vd = Input(UInt(vlen.W)) 54 val vl = Input(Vl()) 55 } 56 val out = new Bundle { 57 val vd = Output(UInt(vlen.W)) 58 } 59} 60