1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import utility._ 23import xiangshan._ 24import xiangshan.backend._ 25 26trait HasCSRConst { 27 28 // User Trap Setup 29 val Ustatus = 0x000 30 val Uie = 0x004 31 val Utvec = 0x005 32 33 // User Trap Handling 34 val Uscratch = 0x040 35 val Uepc = 0x041 36 val Ucause = 0x042 37 val Utval = 0x043 38 val Uip = 0x044 39 40 // User Floating-Point CSRs (not implemented) 41 val Fflags = 0x001 42 val Frm = 0x002 43 val Fcsr = 0x003 44 45 // Vector Extension CSRs 46 val Vstart = 0x008 47 val Vxsat = 0x009 48 val Vxrm = 0x00A 49 val Vcsr = 0x00F 50 val Vl = 0xC20 51 val Vtype = 0xC21 52 val Vlenb = 0xC22 53 54 // User Counter/Timers 55 val Cycle = 0xC00 56 val Time = 0xC01 57 val Instret = 0xC02 58 val Hpmcounter3 = 0xC03 59 val Hpmcounter4 = 0xC04 60 val Hpmcounter5 = 0xC05 61 val Hpmcounter6 = 0xC06 62 val Hpmcounter7 = 0xC07 63 val Hpmcounter8 = 0xC08 64 val Hpmcounter9 = 0xC09 65 val Hpmcounter10 = 0xC0A 66 val Hpmcounter11 = 0xC0B 67 val Hpmcounter12 = 0xC0C 68 val Hpmcounter13 = 0xC0D 69 val Hpmcounter14 = 0xC0E 70 val Hpmcounter15 = 0xC0F 71 val Hpmcounter16 = 0xC10 72 val Hpmcounter17 = 0xC11 73 val Hpmcounter18 = 0xC12 74 val Hpmcounter19 = 0xC13 75 val Hpmcounter20 = 0xC14 76 val Hpmcounter21 = 0xC15 77 val Hpmcounter22 = 0xC16 78 val Hpmcounter23 = 0xC17 79 val Hpmcounter24 = 0xC18 80 val Hpmcounter25 = 0xC19 81 val Hpmcounter26 = 0xC1A 82 val Hpmcounter27 = 0xC1B 83 val Hpmcounter28 = 0xC1C 84 val Hpmcounter29 = 0xC1D 85 val Hpmcounter30 = 0xC1E 86 val Hpmcounter31 = 0xC1F 87 88 // Supervisor Trap Setup 89 val Sstatus = 0x100 90 val Sedeleg = 0x102 91 val Sideleg = 0x103 92 val Sie = 0x104 93 val Stvec = 0x105 94 val Scounteren = 0x106 95 96 // Supervisor Trap Handling 97 val Sscratch = 0x140 98 val Sepc = 0x141 99 val Scause = 0x142 100 val Stval = 0x143 101 val Sip = 0x144 102 103 // Supervisor Protection and Translation 104 val Satp = 0x180 105 106 // Supervisor Custom Read/Write 107 val Sbpctl = 0x5C0 108 val Spfctl = 0x5C1 109 val Slvpredctl = 0x5C2 110 val Smblockctl = 0x5C3 111 val Srnctl = 0x5C4 112 val Scachebase = 0x5C5 113 val Sfetchctl = 0x5C6 114 115 /** 0x5C5-0x5E5 for cache instruction register*/ 116 117 val Sdsid = 0x9C0 118 119 // Machine Information Registers 120 val Mvendorid = 0xF11 121 val Marchid = 0xF12 122 val Mimpid = 0xF13 123 val Mhartid = 0xF14 124 val Mconfigptr = 0xF15 125 126 // Machine Trap Setup 127 val Mstatus = 0x300 128 val Misa = 0x301 129 val Medeleg = 0x302 130 val Mideleg = 0x303 131 val Mie = 0x304 132 val Mtvec = 0x305 133 val Mcounteren = 0x306 134 135 // Machine Trap Handling 136 val Mscratch = 0x340 137 val Mepc = 0x341 138 val Mcause = 0x342 139 val Mtval = 0x343 140 val Mip = 0x344 141 142 // Machine Memory Protection 143 // TBD 144 val PmpcfgBase = 0x3A0 145 val PmpaddrBase = 0x3B0 146 // Machine level PMA 147 val PmacfgBase = 0x7C0 148 val PmaaddrBase = 0x7C8 // 64 entry at most 149 150 // Machine Counter/Timers 151 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 152 // 0xB80 - 0x89F are also used as perfcnt csr 153 val Mcycle = 0xb00 154 val Minstret = 0xb02 155 156 val Mhpmcounter3 = 0xB03 157 val Mhpmcounter4 = 0xB04 158 val Mhpmcounter5 = 0xB05 159 val Mhpmcounter6 = 0xB06 160 val Mhpmcounter7 = 0xB07 161 val Mhpmcounter8 = 0xB08 162 val Mhpmcounter9 = 0xB09 163 val Mhpmcounter10 = 0xB0A 164 val Mhpmcounter11 = 0xB0B 165 val Mhpmcounter12 = 0xB0C 166 val Mhpmcounter13 = 0xB0D 167 val Mhpmcounter14 = 0xB0E 168 val Mhpmcounter15 = 0xB0F 169 val Mhpmcounter16 = 0xB10 170 val Mhpmcounter17 = 0xB11 171 val Mhpmcounter18 = 0xB12 172 val Mhpmcounter19 = 0xB13 173 val Mhpmcounter20 = 0xB14 174 val Mhpmcounter21 = 0xB15 175 val Mhpmcounter22 = 0xB16 176 val Mhpmcounter23 = 0xB17 177 val Mhpmcounter24 = 0xB18 178 val Mhpmcounter25 = 0xB19 179 val Mhpmcounter26 = 0xB1A 180 val Mhpmcounter27 = 0xB1B 181 val Mhpmcounter28 = 0xB1C 182 val Mhpmcounter29 = 0xB1D 183 val Mhpmcounter30 = 0xB1E 184 val Mhpmcounter31 = 0xB1F 185 186 val Mcountinhibit = 0x320 187 val Mhpmevent3 = 0x323 188 val Mhpmevent4 = 0x324 189 val Mhpmevent5 = 0x325 190 val Mhpmevent6 = 0x326 191 val Mhpmevent7 = 0x327 192 val Mhpmevent8 = 0x328 193 val Mhpmevent9 = 0x329 194 val Mhpmevent10 = 0x32A 195 val Mhpmevent11 = 0x32B 196 val Mhpmevent12 = 0x32C 197 val Mhpmevent13 = 0x32D 198 val Mhpmevent14 = 0x32E 199 val Mhpmevent15 = 0x32F 200 val Mhpmevent16 = 0x330 201 val Mhpmevent17 = 0x331 202 val Mhpmevent18 = 0x332 203 val Mhpmevent19 = 0x333 204 val Mhpmevent20 = 0x334 205 val Mhpmevent21 = 0x335 206 val Mhpmevent22 = 0x336 207 val Mhpmevent23 = 0x337 208 val Mhpmevent24 = 0x338 209 val Mhpmevent25 = 0x339 210 val Mhpmevent26 = 0x33A 211 val Mhpmevent27 = 0x33B 212 val Mhpmevent28 = 0x33C 213 val Mhpmevent29 = 0x33D 214 val Mhpmevent30 = 0x33E 215 val Mhpmevent31 = 0x33F 216 217 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 218 219 // Trigger Registers 220 val Tselect = 0x7A0 221 val Tdata1 = 0x7A1 222 val Tdata2 = 0x7A2 223 val Tinfo = 0x7A4 224 val Tcontrol = 0x7A5 225 226 // Debug Mode Registers 227 val Dcsr = 0x7B0 228 val Dpc = 0x7B1 229 val Dscratch0 = 0x7B2 230 val Dscratch1 = 0x7B3 231 232 def privEcall = 0x000.U 233 def privEbreak = 0x001.U 234 def privMret = 0x302.U 235 def privSret = 0x102.U 236 def privUret = 0x002.U 237 def privDret = 0x7b2.U 238 239 def ModeM = 0x3.U 240 def ModeH = 0x2.U 241 def ModeS = 0x1.U 242 def ModeU = 0x0.U 243 244 def IRQ_UEIP = 0 245 def IRQ_SEIP = 1 246 def IRQ_MEIP = 3 247 248 def IRQ_UTIP = 4 249 def IRQ_STIP = 5 250 def IRQ_MTIP = 7 251 252 def IRQ_USIP = 8 253 def IRQ_SSIP = 9 254 def IRQ_MSIP = 11 255 256 def IRQ_DEBUG = 12 257 258 val Satp_Mode_len = 4 259 val Satp_Asid_len = 16 260 val Satp_Addr_len = 44 261 def satp_part_wmask(max_length: Int, length: Int) : UInt = { 262 require(length > 0 && length <= max_length) 263 ((1L << length) - 1).U(max_length.W) 264 } 265 266 val IntPriority = Seq( 267 IRQ_DEBUG, 268 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 269 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 270 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 271 ) 272 273 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 274 val readOnly = addr(11,10) === "b11".U 275 val lowestAccessPrivilegeLevel = addr(9,8) 276 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 277 } 278 279 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 280 val index = UIntToOH(addr & 31.U) 281 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 282 } 283 284 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 285 // debug mode write only regs 286 val isDebugReg = addr(11, 4) === "h7b".U 287 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 288 } 289 290 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 291 val isTriggerReg = addr(11, 4) === "h7a".U 292 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 293 } 294} 295object CSRConst extends HasCSRConst