1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import utility._ 23import xiangshan._ 24import xiangshan.backend._ 25 26trait HasCSRConst { 27 28 // User Trap Setup 29 val Ustatus = 0x000 30 val Uie = 0x004 31 val Utvec = 0x005 32 33 // User Trap Handling 34 val Uscratch = 0x040 35 val Uepc = 0x041 36 val Ucause = 0x042 37 val Utval = 0x043 38 val Uip = 0x044 39 40 // User Floating-Point CSRs (not implemented) 41 val Fflags = 0x001 42 val Frm = 0x002 43 val Fcsr = 0x003 44 45 // User Counter/Timers 46 val Cycle = 0xC00 47 val Time = 0xC01 48 val Instret = 0xC02 49 50 // Supervisor Trap Setup 51 val Sstatus = 0x100 52 val Sedeleg = 0x102 53 val Sideleg = 0x103 54 val Sie = 0x104 55 val Stvec = 0x105 56 val Scounteren = 0x106 57 58 // Supervisor Configuration 59 val Senvcfg = 0x10A 60 61 // Supervisor Trap Handling 62 val Sscratch = 0x140 63 val Sepc = 0x141 64 val Scause = 0x142 65 val Stval = 0x143 66 val Sip = 0x144 67 68 // Supervisor Protection and Translation 69 val Satp = 0x180 70 71 // Supervisor Custom Read/Write 72 val Sbpctl = 0x5C0 73 val Spfctl = 0x5C1 74 val Slvpredctl = 0x5C2 75 val Smblockctl = 0x5C3 76 val Srnctl = 0x5C4 77 /** 0x5C5-0x5E5 for cache instruction register*/ 78 val Scachebase = 0x5C5 79 80 // Supervisor Custom Read/Write 81 val Sdsid = 0x9C0 82 val Sfetchctl = 0x9e0 83 84 // Machine Information Registers 85 val Mvendorid = 0xF11 86 val Marchid = 0xF12 87 val Mimpid = 0xF13 88 val Mhartid = 0xF14 89 val Mconfigptr = 0xF15 90 91 // Machine Trap Setup 92 val Mstatus = 0x300 93 val Misa = 0x301 94 val Medeleg = 0x302 95 val Mideleg = 0x303 96 val Mie = 0x304 97 val Mtvec = 0x305 98 val Mcounteren = 0x306 99 100 // Machine Trap Handling 101 val Mscratch = 0x340 102 val Mepc = 0x341 103 val Mcause = 0x342 104 val Mtval = 0x343 105 val Mip = 0x344 106 107 // Machine Configuration 108 val Menvcfg = 0x30A 109 110 // Machine Memory Protection 111 // TBD 112 val PmpcfgBase = 0x3A0 113 val PmpaddrBase = 0x3B0 114 // Machine level PMA 115 val PmacfgBase = 0x7C0 116 val PmaaddrBase = 0x7C8 // 64 entry at most 117 118 // Machine Counter/Timers 119 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 120 // 0xB80 - 0x89F are also used as perfcnt csr 121 val Mcycle = 0xb00 122 val Minstret = 0xb02 123 124 val Mhpmcounter3 = 0xB03 125 val Mhpmcounter4 = 0xB04 126 val Mhpmcounter5 = 0xB05 127 val Mhpmcounter6 = 0xB06 128 val Mhpmcounter7 = 0xB07 129 val Mhpmcounter8 = 0xB08 130 val Mhpmcounter9 = 0xB09 131 val Mhpmcounter10 = 0xB0A 132 val Mhpmcounter11 = 0xB0B 133 val Mhpmcounter12 = 0xB0C 134 val Mhpmcounter13 = 0xB0D 135 val Mhpmcounter14 = 0xB0E 136 val Mhpmcounter15 = 0xB0F 137 val Mhpmcounter16 = 0xB10 138 val Mhpmcounter17 = 0xB11 139 val Mhpmcounter18 = 0xB12 140 val Mhpmcounter19 = 0xB13 141 val Mhpmcounter20 = 0xB14 142 val Mhpmcounter21 = 0xB15 143 val Mhpmcounter22 = 0xB16 144 val Mhpmcounter23 = 0xB17 145 val Mhpmcounter24 = 0xB18 146 val Mhpmcounter25 = 0xB19 147 val Mhpmcounter26 = 0xB1A 148 val Mhpmcounter27 = 0xB1B 149 val Mhpmcounter28 = 0xB1C 150 val Mhpmcounter29 = 0xB1D 151 val Mhpmcounter30 = 0xB1E 152 val Mhpmcounter31 = 0xB1F 153 154 val Mcountinhibit = 0x320 155 val Mhpmevent3 = 0x323 156 val Mhpmevent4 = 0x324 157 val Mhpmevent5 = 0x325 158 val Mhpmevent6 = 0x326 159 val Mhpmevent7 = 0x327 160 val Mhpmevent8 = 0x328 161 val Mhpmevent9 = 0x329 162 val Mhpmevent10 = 0x32A 163 val Mhpmevent11 = 0x32B 164 val Mhpmevent12 = 0x32C 165 val Mhpmevent13 = 0x32D 166 val Mhpmevent14 = 0x32E 167 val Mhpmevent15 = 0x32F 168 val Mhpmevent16 = 0x330 169 val Mhpmevent17 = 0x331 170 val Mhpmevent18 = 0x332 171 val Mhpmevent19 = 0x333 172 val Mhpmevent20 = 0x334 173 val Mhpmevent21 = 0x335 174 val Mhpmevent22 = 0x336 175 val Mhpmevent23 = 0x337 176 val Mhpmevent24 = 0x338 177 val Mhpmevent25 = 0x339 178 val Mhpmevent26 = 0x33A 179 val Mhpmevent27 = 0x33B 180 val Mhpmevent28 = 0x33C 181 val Mhpmevent29 = 0x33D 182 val Mhpmevent30 = 0x33E 183 val Mhpmevent31 = 0x33F 184 185 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 186 187 // Trigger Registers 188 val Tselect = 0x7A0 189 val Tdata1 = 0x7A1 190 val Tdata2 = 0x7A2 191 val Tinfo = 0x7A4 192 val Tcontrol = 0x7A5 193 194 // Debug Mode Registers 195 val Dcsr = 0x7B0 196 val Dpc = 0x7B1 197 val Dscratch0 = 0x7B2 198 val Dscratch1 = 0x7B3 199 200 def privEcall = 0x000.U 201 def privEbreak = 0x001.U 202 def privMret = 0x302.U 203 def privSret = 0x102.U 204 def privUret = 0x002.U 205 def privDret = 0x7b2.U 206 207 def ModeM = 0x3.U 208 def ModeH = 0x2.U 209 def ModeS = 0x1.U 210 def ModeU = 0x0.U 211 212 def IRQ_USIP = 0 213 def IRQ_SSIP = 1 214 def IRQ_MSIP = 3 215 216 def IRQ_UTIP = 4 217 def IRQ_STIP = 5 218 def IRQ_MTIP = 7 219 220 def IRQ_UEIP = 8 221 def IRQ_SEIP = 9 222 def IRQ_MEIP = 11 223 224 def IRQ_DEBUG = 12 225 226 val Satp_Mode_len = 4 227 val Satp_Asid_len = 16 228 val Satp_Addr_len = 44 229 def satp_part_wmask(max_length: Int, length: Int) : UInt = { 230 require(length > 0 && length <= max_length) 231 ((1L << length) - 1).U(max_length.W) 232 } 233 234 val IntPriority = Seq( 235 IRQ_DEBUG, 236 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 237 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 238 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 239 ) 240 241 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 242 val readOnly = addr(11,10) === "b11".U 243 val lowestAccessPrivilegeLevel = addr(9,8) 244 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 245 } 246 247 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 248 val index = UIntToOH(addr & 31.U) 249 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 250 } 251 252 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 253 // debug mode write only regs 254 val isDebugReg = addr(11, 4) === "h7b".U 255 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 256 } 257 258 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 259 val isTriggerReg = addr(11, 4) === "h7a".U 260 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 261 } 262} 263