1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import xiangshan._ 23import xiangshan.backend._ 24import utils.XSDebug 25 26trait HasCSRConst { 27 28 // User Trap Setup 29 val Ustatus = 0x000 30 val Uie = 0x004 31 val Utvec = 0x005 32 33 // User Trap Handling 34 val Uscratch = 0x040 35 val Uepc = 0x041 36 val Ucause = 0x042 37 val Utval = 0x043 38 val Uip = 0x044 39 40 // User Floating-Point CSRs (not implemented) 41 val Fflags = 0x001 42 val Frm = 0x002 43 val Fcsr = 0x003 44 45 // User Counter/Timers 46 val Cycle = 0xC00 47 val Time = 0xC01 48 val Instret = 0xC02 49 50 // Supervisor Trap Setup 51 val Sstatus = 0x100 52 val Sedeleg = 0x102 53 val Sideleg = 0x103 54 val Sie = 0x104 55 val Stvec = 0x105 56 val Scounteren = 0x106 57 58 // Supervisor Trap Handling 59 val Sscratch = 0x140 60 val Sepc = 0x141 61 val Scause = 0x142 62 val Stval = 0x143 63 val Sip = 0x144 64 65 // Supervisor Protection and Translation 66 val Satp = 0x180 67 68 // Supervisor Custom Read/Write 69 val Sbpctl = 0x5C0 70 val Spfctl = 0x5C1 71 val Slvpredctl = 0x5C2 72 val Smblockctl = 0x5C3 73 val Srnctl = 0x5C4 74 val Scachebase = 0x5C5 75 /** 0x5C5-0x5E5 for cache instruction register*/ 76 77 val Sdsid = 0x9C0 78 79 // Machine Information Registers 80 val Mvendorid = 0xF11 81 val Marchid = 0xF12 82 val Mimpid = 0xF13 83 val Mhartid = 0xF14 84 val Mconfigptr = 0xF15 85 86 // Machine Trap Setup 87 val Mstatus = 0x300 88 val Misa = 0x301 89 val Medeleg = 0x302 90 val Mideleg = 0x303 91 val Mie = 0x304 92 val Mtvec = 0x305 93 val Mcounteren = 0x306 94 95 // Machine Trap Handling 96 val Mscratch = 0x340 97 val Mepc = 0x341 98 val Mcause = 0x342 99 val Mtval = 0x343 100 val Mip = 0x344 101 102 // Machine Memory Protection 103 // TBD 104 val PmpcfgBase = 0x3A0 105 val PmpaddrBase = 0x3B0 106 // Machine level PMA 107 val PmacfgBase = 0x7C0 108 val PmaaddrBase = 0x7C8 // 64 entry at most 109 110 // Machine Counter/Timers 111 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 112 // 0xB80 - 0x89F are also used as perfcnt csr 113 val Mcycle = 0xb00 114 val Minstret = 0xb02 115 116 val Mhpmcounter3 = 0xB03 117 val Mhpmcounter4 = 0xB04 118 val Mhpmcounter5 = 0xB05 119 val Mhpmcounter6 = 0xB06 120 val Mhpmcounter7 = 0xB07 121 val Mhpmcounter8 = 0xB08 122 val Mhpmcounter9 = 0xB09 123 val Mhpmcounter10 = 0xB0A 124 val Mhpmcounter11 = 0xB0B 125 val Mhpmcounter12 = 0xB0C 126 val Mhpmcounter13 = 0xB0D 127 val Mhpmcounter14 = 0xB0E 128 val Mhpmcounter15 = 0xB0F 129 val Mhpmcounter16 = 0xB10 130 val Mhpmcounter17 = 0xB11 131 val Mhpmcounter18 = 0xB12 132 val Mhpmcounter19 = 0xB13 133 val Mhpmcounter20 = 0xB14 134 val Mhpmcounter21 = 0xB15 135 val Mhpmcounter22 = 0xB16 136 val Mhpmcounter23 = 0xB17 137 val Mhpmcounter24 = 0xB18 138 val Mhpmcounter25 = 0xB19 139 val Mhpmcounter26 = 0xB1A 140 val Mhpmcounter27 = 0xB1B 141 val Mhpmcounter28 = 0xB1C 142 val Mhpmcounter29 = 0xB1D 143 val Mhpmcounter30 = 0xB1E 144 val Mhpmcounter31 = 0xB1F 145 146 val Mcountinhibit = 0x320 147 val Mhpmevent3 = 0x323 148 val Mhpmevent4 = 0x324 149 val Mhpmevent5 = 0x325 150 val Mhpmevent6 = 0x326 151 val Mhpmevent7 = 0x327 152 val Mhpmevent8 = 0x328 153 val Mhpmevent9 = 0x329 154 val Mhpmevent10 = 0x32A 155 val Mhpmevent11 = 0x32B 156 val Mhpmevent12 = 0x32C 157 val Mhpmevent13 = 0x32D 158 val Mhpmevent14 = 0x32E 159 val Mhpmevent15 = 0x32F 160 val Mhpmevent16 = 0x330 161 val Mhpmevent17 = 0x331 162 val Mhpmevent18 = 0x332 163 val Mhpmevent19 = 0x333 164 val Mhpmevent20 = 0x334 165 val Mhpmevent21 = 0x335 166 val Mhpmevent22 = 0x336 167 val Mhpmevent23 = 0x337 168 val Mhpmevent24 = 0x338 169 val Mhpmevent25 = 0x339 170 val Mhpmevent26 = 0x33A 171 val Mhpmevent27 = 0x33B 172 val Mhpmevent28 = 0x33C 173 val Mhpmevent29 = 0x33D 174 val Mhpmevent30 = 0x33E 175 val Mhpmevent31 = 0x33F 176 177 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 178 179 // Trigger Registers 180 val Tselect = 0x7A0 181 val Tdata1 = 0x7A1 182 val Tdata2 = 0x7A2 183 val Tinfo = 0x7A4 184 val Tcontrol = 0x7A5 185 186 // Debug Mode Registers 187 val Dcsr = 0x7B0 188 val Dpc = 0x7B1 189 val Dscratch = 0x7B2 190 val Dscratch1 = 0x7B3 191 192 def privEcall = 0x000.U 193 def privEbreak = 0x001.U 194 def privMret = 0x302.U 195 def privSret = 0x102.U 196 def privUret = 0x002.U 197 def privDret = 0x7b2.U 198 199 def ModeM = 0x3.U 200 def ModeH = 0x2.U 201 def ModeS = 0x1.U 202 def ModeU = 0x0.U 203 204 def IRQ_UEIP = 0 205 def IRQ_SEIP = 1 206 def IRQ_MEIP = 3 207 208 def IRQ_UTIP = 4 209 def IRQ_STIP = 5 210 def IRQ_MTIP = 7 211 212 def IRQ_USIP = 8 213 def IRQ_SSIP = 9 214 def IRQ_MSIP = 11 215 216 def IRQ_DEBUG = 12 217 218 val Asid_true_len = 16 219 220 def Asid_true_mask(AsidLength : Int) : UInt = { 221 val res = Wire(Vec(Asid_true_len,Bool())) 222 (0 until Asid_true_len).map(i => { 223 res(i) := (i <= AsidLength).B 224 }) 225 Cat(res.reverse) 226 // val zero = "h0".U(1.W) 227 // val one = "h1".U(1.W) 228 // val mask_high = Fill(Asid_true_len - AsidLength, zero) 229 // val mask_low = Fill(AsidLength, one) 230 231 // Cat(mask_high, mask_low) 232 } 233 234 val IntPriority = Seq( 235 IRQ_DEBUG, 236 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 237 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 238 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 239 ) 240 241 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 242 val readOnly = addr(11,10) === "b11".U 243 val lowestAccessPrivilegeLevel = addr(9,8) 244 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 245 } 246 247 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 248 val index = UIntToOH(addr & 31.U) 249 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 250 } 251 252 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 253 // debug mode write only regs 254 val isDebugReg = addr(11, 4) === "h7b".U 255 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 256 } 257 258 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 259 val isTriggerReg = addr(11, 4) === "h7a".U 260 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 261 } 262} 263