1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import xiangshan._ 23import xiangshan.backend._ 24import utils.XSDebug 25 26trait HasCSRConst { 27 28 // User Trap Setup 29 val Ustatus = 0x000 30 val Uie = 0x004 31 val Utvec = 0x005 32 33 // User Trap Handling 34 val Uscratch = 0x040 35 val Uepc = 0x041 36 val Ucause = 0x042 37 val Utval = 0x043 38 val Uip = 0x044 39 40 // User Floating-Point CSRs (not implemented) 41 val Fflags = 0x001 42 val Frm = 0x002 43 val Fcsr = 0x003 44 45 // User Counter/Timers 46 val Cycle = 0xC00 47 val Time = 0xC01 48 val Instret = 0xC02 49 50 // Supervisor Trap Setup 51 val Sstatus = 0x100 52 val Sedeleg = 0x102 53 val Sideleg = 0x103 54 val Sie = 0x104 55 val Stvec = 0x105 56 val Scounteren = 0x106 57 58 // Supervisor Trap Handling 59 val Sscratch = 0x140 60 val Sepc = 0x141 61 val Scause = 0x142 62 val Stval = 0x143 63 val Sip = 0x144 64 65 // Supervisor Protection and Translation 66 val Satp = 0x180 67 68 // Supervisor Custom Read/Write 69 val Sbpctl = 0x5C0 70 val Spfctl = 0x5C1 71 val Slvpredctl = 0x5C2 72 val Smblockctl = 0x5C3 73 val Srnctl = 0x5C4 74 75 val Sdsid = 0x9C0 76 77 // Machine Information Registers 78 val Mvendorid = 0xF11 79 val Marchid = 0xF12 80 val Mimpid = 0xF13 81 val Mhartid = 0xF14 82 83 // Machine Trap Setup 84 val Mstatus = 0x300 85 val Misa = 0x301 86 val Medeleg = 0x302 87 val Mideleg = 0x303 88 val Mie = 0x304 89 val Mtvec = 0x305 90 val Mcounteren = 0x306 91 92 // Machine Trap Handling 93 val Mscratch = 0x340 94 val Mepc = 0x341 95 val Mcause = 0x342 96 val Mtval = 0x343 97 val Mip = 0x344 98 99 // Machine Memory Protection 100 // TBD 101 val Pmpcfg0 = 0x3A0 102 val Pmpcfg1 = 0x3A1 103 val Pmpcfg2 = 0x3A2 104 val Pmpcfg3 = 0x3A3 105 val PmpaddrBase = 0x3B0 106 107 // Machine Counter/Timers 108 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 109 // 0xB80 - 0x89F are also used as perfcnt csr 110 val Mcycle = 0xb00 111 val Minstret = 0xb02 112 113 val Mhpmcounter3 = 0xB03 114 val Mhpmcounter4 = 0xB04 115 val Mhpmcounter5 = 0xB05 116 val Mhpmcounter6 = 0xB06 117 val Mhpmcounter7 = 0xB07 118 val Mhpmcounter8 = 0xB08 119 val Mhpmcounter9 = 0xB09 120 val Mhpmcounter10 = 0xB0A 121 val Mhpmcounter11 = 0xB0B 122 val Mhpmcounter12 = 0xB0C 123 val Mhpmcounter13 = 0xB0D 124 val Mhpmcounter14 = 0xB0E 125 val Mhpmcounter15 = 0xB0F 126 val Mhpmcounter16 = 0xB10 127 val Mhpmcounter17 = 0xB11 128 val Mhpmcounter18 = 0xB12 129 val Mhpmcounter19 = 0xB13 130 val Mhpmcounter20 = 0xB14 131 val Mhpmcounter21 = 0xB15 132 val Mhpmcounter22 = 0xB16 133 val Mhpmcounter23 = 0xB17 134 val Mhpmcounter24 = 0xB18 135 val Mhpmcounter25 = 0xB19 136 val Mhpmcounter26 = 0xB1A 137 val Mhpmcounter27 = 0xB1B 138 val Mhpmcounter28 = 0xB1C 139 val Mhpmcounter29 = 0xB1D 140 val Mhpmcounter30 = 0xB1E 141 val Mhpmcounter31 = 0xB1F 142 143 // Machine Counter Setup (not implemented) 144 val Mcountinhibit = 0x320 145 val Mhpmevent3 = 0x323 146 val Mhpmevent4 = 0x324 147 val Mhpmevent5 = 0x325 148 val Mhpmevent6 = 0x326 149 val Mhpmevent7 = 0x327 150 val Mhpmevent8 = 0x328 151 val Mhpmevent9 = 0x329 152 val Mhpmevent10 = 0x32A 153 val Mhpmevent11 = 0x32B 154 val Mhpmevent12 = 0x32C 155 val Mhpmevent13 = 0x32D 156 val Mhpmevent14 = 0x32E 157 val Mhpmevent15 = 0x32F 158 val Mhpmevent16 = 0x330 159 val Mhpmevent17 = 0x331 160 val Mhpmevent18 = 0x332 161 val Mhpmevent19 = 0x333 162 val Mhpmevent20 = 0x334 163 val Mhpmevent21 = 0x335 164 val Mhpmevent22 = 0x336 165 val Mhpmevent23 = 0x337 166 val Mhpmevent24 = 0x338 167 val Mhpmevent25 = 0x339 168 val Mhpmevent26 = 0x33A 169 val Mhpmevent27 = 0x33B 170 val Mhpmevent28 = 0x33C 171 val Mhpmevent29 = 0x33D 172 val Mhpmevent30 = 0x33E 173 val Mhpmevent31 = 0x33F 174 175 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 176 // Debug Mode Registers 177 val Dcsr = 0x7B0 178 val Dpc = 0x7B1 179 val Dscratch = 0x7B2 180 val Dscratch1 = 0x7B3 181 182 def privEcall = 0x000.U 183 def privEbreak = 0x001.U 184 def privMret = 0x302.U 185 def privSret = 0x102.U 186 def privUret = 0x002.U 187 def privDret = 0x7b2.U 188 189 def ModeM = 0x3.U 190 def ModeH = 0x2.U 191 def ModeS = 0x1.U 192 def ModeU = 0x0.U 193 194 def IRQ_UEIP = 0 195 def IRQ_SEIP = 1 196 def IRQ_MEIP = 3 197 198 def IRQ_UTIP = 4 199 def IRQ_STIP = 5 200 def IRQ_MTIP = 7 201 202 def IRQ_USIP = 8 203 def IRQ_SSIP = 9 204 def IRQ_MSIP = 11 205 206 def IRQ_DEBUG = 12 207 208 val IntPriority = Seq( 209 IRQ_DEBUG, 210 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 211 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 212 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 213 ) 214 215 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 216 val readOnly = addr(11,10) === "b11".U 217 val lowestAccessPrivilegeLevel = addr(9,8) 218 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 219 } 220 221 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 222 val index = UIntToOH(addr & 31.U) 223 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 224 } 225} 226