1package xiangshan.backend.fu.util 2 3import chisel3._ 4import chisel3.ExcitingUtils.{ConnectionType, Debug} 5import chisel3.util._ 6import utils._ 7import xiangshan._ 8import xiangshan.backend._ 9import utils.XSDebug 10 11trait HasCSRConst { 12 13 // User Trap Setup 14 val Ustatus = 0x000 15 val Uie = 0x004 16 val Utvec = 0x005 17 18 // User Trap Handling 19 val Uscratch = 0x040 20 val Uepc = 0x041 21 val Ucause = 0x042 22 val Utval = 0x043 23 val Uip = 0x044 24 25 // User Floating-Point CSRs (not implemented) 26 val Fflags = 0x001 27 val Frm = 0x002 28 val Fcsr = 0x003 29 30 // User Counter/Timers 31 val Cycle = 0xC00 32 val Time = 0xC01 33 val Instret = 0xC02 34 35 // Supervisor Trap Setup 36 val Sstatus = 0x100 37 val Sedeleg = 0x102 38 val Sideleg = 0x103 39 val Sie = 0x104 40 val Stvec = 0x105 41 val Scounteren = 0x106 42 43 // Supervisor Trap Handling 44 val Sscratch = 0x140 45 val Sepc = 0x141 46 val Scause = 0x142 47 val Stval = 0x143 48 val Sip = 0x144 49 50 // Supervisor Protection and Translation 51 val Satp = 0x180 52 53 // Supervisor Custom Read/Write 54 val Sbpctl = 0x5C0 55 val Spfctl = 0x5C1 56 57 val Sdsid = 0x9C0 58 59 // Machine Information Registers 60 val Mvendorid = 0xF11 61 val Marchid = 0xF12 62 val Mimpid = 0xF13 63 val Mhartid = 0xF14 64 65 // Machine Trap Setup 66 val Mstatus = 0x300 67 val Misa = 0x301 68 val Medeleg = 0x302 69 val Mideleg = 0x303 70 val Mie = 0x304 71 val Mtvec = 0x305 72 val Mcounteren = 0x306 73 74 // Machine Trap Handling 75 val Mscratch = 0x340 76 val Mepc = 0x341 77 val Mcause = 0x342 78 val Mtval = 0x343 79 val Mip = 0x344 80 81 // Machine Memory Protection 82 // TBD 83 val Pmpcfg0 = 0x3A0 84 val Pmpcfg1 = 0x3A1 85 val Pmpcfg2 = 0x3A2 86 val Pmpcfg3 = 0x3A3 87 val PmpaddrBase = 0x3B0 88 89 // Machine Counter/Timers 90 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 91 // 0xB80 - 0x89F are also used as perfcnt csr 92 val Mcycle = 0xb00 93 val Minstret = 0xb02 94 95 val Mhpmcounter3 = 0xB03 96 val Mhpmcounter4 = 0xB04 97 val Mhpmcounter5 = 0xB05 98 val Mhpmcounter6 = 0xB06 99 val Mhpmcounter7 = 0xB07 100 val Mhpmcounter8 = 0xB08 101 val Mhpmcounter9 = 0xB09 102 val Mhpmcounter10 = 0xB0A 103 val Mhpmcounter11 = 0xB0B 104 val Mhpmcounter12 = 0xB0C 105 val Mhpmcounter13 = 0xB0D 106 val Mhpmcounter14 = 0xB0E 107 val Mhpmcounter15 = 0xB0F 108 val Mhpmcounter16 = 0xB10 109 val Mhpmcounter17 = 0xB11 110 val Mhpmcounter18 = 0xB12 111 val Mhpmcounter19 = 0xB13 112 val Mhpmcounter20 = 0xB14 113 val Mhpmcounter21 = 0xB15 114 val Mhpmcounter22 = 0xB16 115 val Mhpmcounter23 = 0xB17 116 val Mhpmcounter24 = 0xB18 117 val Mhpmcounter25 = 0xB19 118 val Mhpmcounter26 = 0xB1A 119 val Mhpmcounter27 = 0xB1B 120 val Mhpmcounter28 = 0xB1C 121 val Mhpmcounter29 = 0xB1D 122 val Mhpmcounter30 = 0xB1E 123 val Mhpmcounter31 = 0xB1F 124 125 // Machine Counter Setup (not implemented) 126 val Mcountinhibit = 0x320 127 val Mhpmevent3 = 0x323 128 val Mhpmevent4 = 0x324 129 val Mhpmevent5 = 0x325 130 val Mhpmevent6 = 0x326 131 val Mhpmevent7 = 0x327 132 val Mhpmevent8 = 0x328 133 val Mhpmevent9 = 0x329 134 val Mhpmevent10 = 0x32A 135 val Mhpmevent11 = 0x32B 136 val Mhpmevent12 = 0x32C 137 val Mhpmevent13 = 0x32D 138 val Mhpmevent14 = 0x32E 139 val Mhpmevent15 = 0x32F 140 val Mhpmevent16 = 0x330 141 val Mhpmevent17 = 0x331 142 val Mhpmevent18 = 0x332 143 val Mhpmevent19 = 0x333 144 val Mhpmevent20 = 0x334 145 val Mhpmevent21 = 0x335 146 val Mhpmevent22 = 0x336 147 val Mhpmevent23 = 0x337 148 val Mhpmevent24 = 0x338 149 val Mhpmevent25 = 0x339 150 val Mhpmevent26 = 0x33A 151 val Mhpmevent27 = 0x33B 152 val Mhpmevent28 = 0x33C 153 val Mhpmevent29 = 0x33D 154 val Mhpmevent30 = 0x33E 155 val Mhpmevent31 = 0x33F 156 157 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 158 // Debug Mode Registers (not implemented) 159 160 def privEcall = 0x000.U 161 def privEbreak = 0x001.U 162 def privMret = 0x302.U 163 def privSret = 0x102.U 164 def privUret = 0x002.U 165 166 def ModeM = 0x3.U 167 def ModeH = 0x2.U 168 def ModeS = 0x1.U 169 def ModeU = 0x0.U 170 171 def IRQ_UEIP = 0 172 def IRQ_SEIP = 1 173 def IRQ_MEIP = 3 174 175 def IRQ_UTIP = 4 176 def IRQ_STIP = 5 177 def IRQ_MTIP = 7 178 179 def IRQ_USIP = 8 180 def IRQ_SSIP = 9 181 def IRQ_MSIP = 11 182 183 val IntPriority = Seq( 184 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 185 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 186 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 187 ) 188 189 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 190 val readOnly = addr(11,10) === "b11".U 191 val lowestAccessPrivilegeLevel = addr(9,8) 192 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 193 } 194 195 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 196 val index = UIntToOH(addr & 31.U) 197 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 198 } 199} 200