1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import utility._ 23import xiangshan._ 24import xiangshan.backend._ 25 26trait HasCSRConst { 27 28 // User Trap Setup 29 val Ustatus = 0x000 30 val Uie = 0x004 31 val Utvec = 0x005 32 33 // User Trap Handling 34 val Uscratch = 0x040 35 val Uepc = 0x041 36 val Ucause = 0x042 37 val Utval = 0x043 38 val Uip = 0x044 39 40 // User Floating-Point CSRs (not implemented) 41 val Fflags = 0x001 42 val Frm = 0x002 43 val Fcsr = 0x003 44 45 // User Counter/Timers 46 val Cycle = 0xC00 47 val Time = 0xC01 48 val Instret = 0xC02 49 50 // Supervisor Trap Setup 51 val Sstatus = 0x100 52 val Sedeleg = 0x102 53 val Sideleg = 0x103 54 val Sie = 0x104 55 val Stvec = 0x105 56 val Scounteren = 0x106 57 58 // Supervisor Trap Handling 59 val Sscratch = 0x140 60 val Sepc = 0x141 61 val Scause = 0x142 62 val Stval = 0x143 63 val Sip = 0x144 64 65 // Supervisor Protection and Translation 66 val Satp = 0x180 67 68 // Supervisor Custom Read/Write 69 val Sbpctl = 0x5C0 70 val Spfctl = 0x5C1 71 val Slvpredctl = 0x5C2 72 val Smblockctl = 0x5C3 73 val Srnctl = 0x5C4 74 /** 0x5C5-0x5E5 for cache instruction register*/ 75 val Scachebase = 0x5C5 76 77 // Supervisor Custom Read/Write 78 val Sdsid = 0x9C0 79 val Sfetchctl = 0x9e0 80 81 // Machine Information Registers 82 val Mvendorid = 0xF11 83 val Marchid = 0xF12 84 val Mimpid = 0xF13 85 val Mhartid = 0xF14 86 val Mconfigptr = 0xF15 87 88 // Machine Trap Setup 89 val Mstatus = 0x300 90 val Misa = 0x301 91 val Medeleg = 0x302 92 val Mideleg = 0x303 93 val Mie = 0x304 94 val Mtvec = 0x305 95 val Mcounteren = 0x306 96 97 // Machine Trap Handling 98 val Mscratch = 0x340 99 val Mepc = 0x341 100 val Mcause = 0x342 101 val Mtval = 0x343 102 val Mip = 0x344 103 104 // Machine Memory Protection 105 // TBD 106 val PmpcfgBase = 0x3A0 107 val PmpaddrBase = 0x3B0 108 // Machine level PMA 109 val PmacfgBase = 0x7C0 110 val PmaaddrBase = 0x7C8 // 64 entry at most 111 112 // Machine Counter/Timers 113 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 114 // 0xB80 - 0x89F are also used as perfcnt csr 115 val Mcycle = 0xb00 116 val Minstret = 0xb02 117 118 val Mhpmcounter3 = 0xB03 119 val Mhpmcounter4 = 0xB04 120 val Mhpmcounter5 = 0xB05 121 val Mhpmcounter6 = 0xB06 122 val Mhpmcounter7 = 0xB07 123 val Mhpmcounter8 = 0xB08 124 val Mhpmcounter9 = 0xB09 125 val Mhpmcounter10 = 0xB0A 126 val Mhpmcounter11 = 0xB0B 127 val Mhpmcounter12 = 0xB0C 128 val Mhpmcounter13 = 0xB0D 129 val Mhpmcounter14 = 0xB0E 130 val Mhpmcounter15 = 0xB0F 131 val Mhpmcounter16 = 0xB10 132 val Mhpmcounter17 = 0xB11 133 val Mhpmcounter18 = 0xB12 134 val Mhpmcounter19 = 0xB13 135 val Mhpmcounter20 = 0xB14 136 val Mhpmcounter21 = 0xB15 137 val Mhpmcounter22 = 0xB16 138 val Mhpmcounter23 = 0xB17 139 val Mhpmcounter24 = 0xB18 140 val Mhpmcounter25 = 0xB19 141 val Mhpmcounter26 = 0xB1A 142 val Mhpmcounter27 = 0xB1B 143 val Mhpmcounter28 = 0xB1C 144 val Mhpmcounter29 = 0xB1D 145 val Mhpmcounter30 = 0xB1E 146 val Mhpmcounter31 = 0xB1F 147 148 val Mcountinhibit = 0x320 149 val Mhpmevent3 = 0x323 150 val Mhpmevent4 = 0x324 151 val Mhpmevent5 = 0x325 152 val Mhpmevent6 = 0x326 153 val Mhpmevent7 = 0x327 154 val Mhpmevent8 = 0x328 155 val Mhpmevent9 = 0x329 156 val Mhpmevent10 = 0x32A 157 val Mhpmevent11 = 0x32B 158 val Mhpmevent12 = 0x32C 159 val Mhpmevent13 = 0x32D 160 val Mhpmevent14 = 0x32E 161 val Mhpmevent15 = 0x32F 162 val Mhpmevent16 = 0x330 163 val Mhpmevent17 = 0x331 164 val Mhpmevent18 = 0x332 165 val Mhpmevent19 = 0x333 166 val Mhpmevent20 = 0x334 167 val Mhpmevent21 = 0x335 168 val Mhpmevent22 = 0x336 169 val Mhpmevent23 = 0x337 170 val Mhpmevent24 = 0x338 171 val Mhpmevent25 = 0x339 172 val Mhpmevent26 = 0x33A 173 val Mhpmevent27 = 0x33B 174 val Mhpmevent28 = 0x33C 175 val Mhpmevent29 = 0x33D 176 val Mhpmevent30 = 0x33E 177 val Mhpmevent31 = 0x33F 178 179 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 180 181 // Trigger Registers 182 val Tselect = 0x7A0 183 val Tdata1 = 0x7A1 184 val Tdata2 = 0x7A2 185 val Tinfo = 0x7A4 186 val Tcontrol = 0x7A5 187 188 // Debug Mode Registers 189 val Dcsr = 0x7B0 190 val Dpc = 0x7B1 191 val Dscratch = 0x7B2 192 val Dscratch1 = 0x7B3 193 194 def privEcall = 0x000.U 195 def privEbreak = 0x001.U 196 def privMret = 0x302.U 197 def privSret = 0x102.U 198 def privUret = 0x002.U 199 def privDret = 0x7b2.U 200 201 def ModeM = 0x3.U 202 def ModeH = 0x2.U 203 def ModeS = 0x1.U 204 def ModeU = 0x0.U 205 206 def IRQ_USIP = 0 207 def IRQ_SSIP = 1 208 def IRQ_MSIP = 3 209 210 def IRQ_UTIP = 4 211 def IRQ_STIP = 5 212 def IRQ_MTIP = 7 213 214 def IRQ_UEIP = 8 215 def IRQ_SEIP = 9 216 def IRQ_MEIP = 11 217 218 def IRQ_DEBUG = 12 219 220 val Satp_Mode_len = 4 221 val Satp_Asid_len = 16 222 val Satp_Addr_len = 44 223 def satp_part_wmask(max_length: Int, length: Int) : UInt = { 224 require(length > 0 && length <= max_length) 225 ((1L << length) - 1).U(max_length.W) 226 } 227 228 val IntPriority = Seq( 229 IRQ_DEBUG, 230 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 231 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 232 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 233 ) 234 235 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 236 val readOnly = addr(11,10) === "b11".U 237 val lowestAccessPrivilegeLevel = addr(9,8) 238 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 239 } 240 241 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 242 val index = UIntToOH(addr & 31.U) 243 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 244 } 245 246 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 247 // debug mode write only regs 248 val isDebugReg = addr(11, 4) === "h7b".U 249 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 250 } 251 252 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 253 val isTriggerReg = addr(11, 4) === "h7a".U 254 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 255 } 256} 257