1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21 22trait HasCSRConst { 23 24 // User Trap Setup 25 val Ustatus = 0x000 26 val Uie = 0x004 27 val Utvec = 0x005 28 29 // User Trap Handling 30 val Uscratch = 0x040 31 val Uepc = 0x041 32 val Ucause = 0x042 33 val Utval = 0x043 34 val Uip = 0x044 35 36 // User Floating-Point CSRs (not implemented) 37 val Fflags = 0x001 38 val Frm = 0x002 39 val Fcsr = 0x003 40 41 // Vector Extension CSRs 42 val Vstart = 0x008 43 val Vxsat = 0x009 44 val Vxrm = 0x00A 45 val Vcsr = 0x00F 46 val Vl = 0xC20 47 val Vtype = 0xC21 48 val Vlenb = 0xC22 49 50 // User Counter/Timers 51 val Cycle = 0xC00 52 val Time = 0xC01 53 val Instret = 0xC02 54 val Hpmcounter3 = 0xC03 55 val Hpmcounter4 = 0xC04 56 val Hpmcounter5 = 0xC05 57 val Hpmcounter6 = 0xC06 58 val Hpmcounter7 = 0xC07 59 val Hpmcounter8 = 0xC08 60 val Hpmcounter9 = 0xC09 61 val Hpmcounter10 = 0xC0A 62 val Hpmcounter11 = 0xC0B 63 val Hpmcounter12 = 0xC0C 64 val Hpmcounter13 = 0xC0D 65 val Hpmcounter14 = 0xC0E 66 val Hpmcounter15 = 0xC0F 67 val Hpmcounter16 = 0xC10 68 val Hpmcounter17 = 0xC11 69 val Hpmcounter18 = 0xC12 70 val Hpmcounter19 = 0xC13 71 val Hpmcounter20 = 0xC14 72 val Hpmcounter21 = 0xC15 73 val Hpmcounter22 = 0xC16 74 val Hpmcounter23 = 0xC17 75 val Hpmcounter24 = 0xC18 76 val Hpmcounter25 = 0xC19 77 val Hpmcounter26 = 0xC1A 78 val Hpmcounter27 = 0xC1B 79 val Hpmcounter28 = 0xC1C 80 val Hpmcounter29 = 0xC1D 81 val Hpmcounter30 = 0xC1E 82 val Hpmcounter31 = 0xC1F 83 84 // Supervisor Trap Setup 85 val Sstatus = 0x100 86 val Sedeleg = 0x102 87 val Sideleg = 0x103 88 val Sie = 0x104 89 val Stvec = 0x105 90 val Scounteren = 0x106 91 92 // Supervisor Configuration 93 val Senvcfg = 0x10A 94 95 // Supervisor Trap Handling 96 val Sscratch = 0x140 97 val Sepc = 0x141 98 val Scause = 0x142 99 val Stval = 0x143 100 val Sip = 0x144 101 102 // Supervisor Protection and Translation 103 val Satp = 0x180 104 105 // Supervisor Custom Read/Write 106 val Sbpctl = 0x5C0 107 val Spfctl = 0x5C1 108 val Slvpredctl = 0x5C2 109 val Smblockctl = 0x5C3 110 val Srnctl = 0x5C4 111 /** 0x5C5-0x5E5 for cache instruction register*/ 112 val Scachebase = 0x5C5 113 114 // Hypervisor Trap Setup 115 val Hstatus = 0x600 116 val Hedeleg = 0x602 117 val Hideleg = 0x603 118 val Hie = 0x604 119 val Hcounteren = 0x606 120 val Hgeie = 0x607 121 122 // Hypervisor Trap Handling 123 val Htval = 0x643 124 val Hip = 0x644 125 val Hvip = 0x645 126 val Htinst = 0x64A 127 val Hgeip = 0xE12 128 129 // Hypervisor Configuration 130 val Henvcfg = 0x60A 131 132 // Hypervisor Protection and Translation 133 val Hgatp = 0x680 134 135 //Hypervisor Counter/Timer Virtualization Registers 136 val Htimedelta = 0x605 137 138 // Virtual Supervisor Registers 139 val Vsstatus = 0x200 140 val Vsie = 0x204 141 val Vstvec = 0x205 142 val Vsscratch = 0x240 143 val Vsepc = 0x241 144 val Vscause = 0x242 145 val Vstval = 0x243 146 val Vsip = 0x244 147 val Vsatp = 0x280 148 149 // Machine Information Registers 150 val Mvendorid = 0xF11 151 val Marchid = 0xF12 152 val Mimpid = 0xF13 153 val Mhartid = 0xF14 154 val Mconfigptr = 0xF15 155 156 // Machine Trap Setup 157 val Mstatus = 0x300 158 val Misa = 0x301 159 val Medeleg = 0x302 160 val Mideleg = 0x303 161 val Mie = 0x304 162 val Mtvec = 0x305 163 val Mcounteren = 0x306 164 165 // Machine Trap Handling 166 val Mscratch = 0x340 167 val Mepc = 0x341 168 val Mcause = 0x342 169 val Mtval = 0x343 170 val Mip = 0x344 171 val Mtinst = 0x34A 172 val Mtval2 = 0x34B 173 174 // Machine Configuration 175 val Menvcfg = 0x30A 176 177 // Machine Memory Protection 178 // TBD 179 val PmpcfgBase = 0x3A0 180 val PmpaddrBase = 0x3B0 181 // Machine level PMA 182 val PmacfgBase = 0x7C0 183 val PmaaddrBase = 0x7C8 // 64 entry at most 184 185 // Machine Counter/Timers 186 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 187 // 0xB80 - 0x89F are also used as perfcnt csr 188 val Mcycle = 0xb00 189 val Minstret = 0xb02 190 191 val Mhpmcounter3 = 0xB03 192 val Mhpmcounter4 = 0xB04 193 val Mhpmcounter5 = 0xB05 194 val Mhpmcounter6 = 0xB06 195 val Mhpmcounter7 = 0xB07 196 val Mhpmcounter8 = 0xB08 197 val Mhpmcounter9 = 0xB09 198 val Mhpmcounter10 = 0xB0A 199 val Mhpmcounter11 = 0xB0B 200 val Mhpmcounter12 = 0xB0C 201 val Mhpmcounter13 = 0xB0D 202 val Mhpmcounter14 = 0xB0E 203 val Mhpmcounter15 = 0xB0F 204 val Mhpmcounter16 = 0xB10 205 val Mhpmcounter17 = 0xB11 206 val Mhpmcounter18 = 0xB12 207 val Mhpmcounter19 = 0xB13 208 val Mhpmcounter20 = 0xB14 209 val Mhpmcounter21 = 0xB15 210 val Mhpmcounter22 = 0xB16 211 val Mhpmcounter23 = 0xB17 212 val Mhpmcounter24 = 0xB18 213 val Mhpmcounter25 = 0xB19 214 val Mhpmcounter26 = 0xB1A 215 val Mhpmcounter27 = 0xB1B 216 val Mhpmcounter28 = 0xB1C 217 val Mhpmcounter29 = 0xB1D 218 val Mhpmcounter30 = 0xB1E 219 val Mhpmcounter31 = 0xB1F 220 221 val Mcountinhibit = 0x320 222 val Mhpmevent3 = 0x323 223 val Mhpmevent4 = 0x324 224 val Mhpmevent5 = 0x325 225 val Mhpmevent6 = 0x326 226 val Mhpmevent7 = 0x327 227 val Mhpmevent8 = 0x328 228 val Mhpmevent9 = 0x329 229 val Mhpmevent10 = 0x32A 230 val Mhpmevent11 = 0x32B 231 val Mhpmevent12 = 0x32C 232 val Mhpmevent13 = 0x32D 233 val Mhpmevent14 = 0x32E 234 val Mhpmevent15 = 0x32F 235 val Mhpmevent16 = 0x330 236 val Mhpmevent17 = 0x331 237 val Mhpmevent18 = 0x332 238 val Mhpmevent19 = 0x333 239 val Mhpmevent20 = 0x334 240 val Mhpmevent21 = 0x335 241 val Mhpmevent22 = 0x336 242 val Mhpmevent23 = 0x337 243 val Mhpmevent24 = 0x338 244 val Mhpmevent25 = 0x339 245 val Mhpmevent26 = 0x33A 246 val Mhpmevent27 = 0x33B 247 val Mhpmevent28 = 0x33C 248 val Mhpmevent29 = 0x33D 249 val Mhpmevent30 = 0x33E 250 val Mhpmevent31 = 0x33F 251 252 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 253 254 // Trigger Registers 255 val Tselect = 0x7A0 256 val Tdata1 = 0x7A1 257 val Tdata2 = 0x7A2 258 val Tinfo = 0x7A4 259 val Tcontrol = 0x7A5 260 261 // Debug Mode Registers 262 val Dcsr = 0x7B0 263 val Dpc = 0x7B1 264 val Dscratch0 = 0x7B2 265 val Dscratch1 = 0x7B3 266 267 /** 268 * "Read only" CSRs that can be fully pipelined when read in CSRR instruction. 269 * Only read by csr instructions. 270 */ 271 val roCsrrAddr = List( 272 Frm, 273 Vxrm, 274 Stvec, 275 Scounteren, 276 Senvcfg, 277 Sscratch, 278 Sepc, 279 Scause, 280 Stval, 281 Satp, 282 Vstvec, 283 Vsscratch, 284 Vsepc, 285 Vscause, 286 Vstval, 287 Vsatp, 288 Medeleg, 289 Mideleg, 290 Mtvec, 291 Mcounteren, 292 Menvcfg, 293 Mcountinhibit, 294 Mscratch, 295 Mepc, 296 Mcause, 297 Mtval, 298 Mtinst, 299 Mtval2, 300 Sbpctl, // customized csr: sbpctl S-mode Branch Prediction ConTroL 301 Spfctl, // customized csr: spfctl S-mode PreFetch ConTroL 302 Slvpredctl, // customized csr: slvpredctl S-mode Load Violation PREDict ConTroL 303 Smblockctl, // customized csr: smblockctl S-mode Memory BlockConTroL 304 Srnctl, // customized csr: srnctl S-mode ? 305 Hedeleg, 306 Hideleg, 307 Hcounteren, 308 Htval, 309 Hgatp, 310 Mvendorid, 311 Marchid, 312 Mimpid, 313 Mhartid, 314 Mconfigptr 315 ) 316 317 def privEcall = 0x000.U 318 def privEbreak = 0x001.U 319 def privMNret = 0x702.U 320 def privMret = 0x302.U 321 def privSret = 0x102.U 322 def privUret = 0x002.U 323 def privDret = 0x7b2.U 324 325 def ModeM = 0x3.U 326 def ModeH = 0x2.U 327 def ModeS = 0x1.U 328 def ModeU = 0x0.U 329 330 def IRQ_USIP = 0 331 def IRQ_SSIP = 1 332 def IRQ_VSSIP = 2 333 def IRQ_MSIP = 3 334 335 def IRQ_UTIP = 4 336 def IRQ_STIP = 5 337 def IRQ_VSTIP = 6 338 def IRQ_MTIP = 7 339 340 def IRQ_UEIP = 8 341 def IRQ_SEIP = 9 342 def IRQ_VSEIP = 10 343 def IRQ_MEIP = 11 344 345 def IRQ_SGEIP = 12 346 def IRQ_DEBUG = 17 347 348 val Hgatp_Mode_len = 4 349 val Hgatp_Vmid_len = 16 350 val Hgatp_Addr_len = 44 351 352 val Satp_Mode_len = 4 353 val Satp_Asid_len = 16 354 val Satp_Addr_len = 44 355 def satp_part_wmask(max_length: Int, length: Int) : UInt = { 356 require(length > 0 && length <= max_length) 357 ((1L << length) - 1).U(max_length.W) 358 } 359 360 val IntPriority = Seq( 361 IRQ_DEBUG, 362 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 363 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 364 IRQ_UEIP, IRQ_USIP, IRQ_UTIP, 365 IRQ_VSEIP, IRQ_VSSIP, IRQ_VSTIP, IRQ_SGEIP 366 ) 367 368 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt, virt: Bool, hasH: Bool): UInt = { 369 val readOnly = addr(11, 10) === "b11".U 370 val lowestAccessPrivilegeLevel = addr(9,8) 371 val priv = Mux(mode === ModeS, ModeH, mode) 372 val ret = Wire(Bool()) //0.U: normal, 1.U: illegal_instruction, 2.U: virtual instruction 373 when (lowestAccessPrivilegeLevel === ModeH && !hasH){ 374 ret := 1.U 375 }.elsewhen (readOnly && wen) { 376 ret := 1.U 377 }.elsewhen (priv < lowestAccessPrivilegeLevel) { 378 when(virt && lowestAccessPrivilegeLevel <= ModeH){ 379 ret := 2.U 380 }.otherwise{ 381 ret := 1.U 382 } 383 }.otherwise{ 384 ret := 0.U 385 } 386 ret 387 } 388 389 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 390 val index = UIntToOH(addr & 31.U) 391 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 392 } 393 394 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 395 // debug mode write only regs 396 val isDebugReg = addr(11, 4) === "h7b".U 397 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 398 } 399 400 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 401 val isTriggerReg = addr(11, 4) === "h7a".U 402 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 403 } 404} 405object CSRConst extends HasCSRConst 406