1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import utility._ 23import xiangshan._ 24import xiangshan.backend._ 25 26trait HasCSRConst { 27 28 // User Trap Setup 29 val Ustatus = 0x000 30 val Uie = 0x004 31 val Utvec = 0x005 32 33 // User Trap Handling 34 val Uscratch = 0x040 35 val Uepc = 0x041 36 val Ucause = 0x042 37 val Utval = 0x043 38 val Uip = 0x044 39 40 // User Floating-Point CSRs (not implemented) 41 val Fflags = 0x001 42 val Frm = 0x002 43 val Fcsr = 0x003 44 45 // Vector Extension CSRs 46 val Vstart = 0x008 47 val Vxsat = 0x009 48 val Vxrm = 0x00A 49 val Vcsr = 0x00F 50 val Vl = 0xC20 51 val Vtype = 0xC21 52 val Vlenb = 0xC22 53 54 // User Counter/Timers 55 val Cycle = 0xC00 56 val Time = 0xC01 57 val Instret = 0xC02 58 val Hpmcounter3 = 0xC03 59 val Hpmcounter4 = 0xC04 60 val Hpmcounter5 = 0xC05 61 val Hpmcounter6 = 0xC06 62 val Hpmcounter7 = 0xC07 63 val Hpmcounter8 = 0xC08 64 val Hpmcounter9 = 0xC09 65 val Hpmcounter10 = 0xC0A 66 val Hpmcounter11 = 0xC0B 67 val Hpmcounter12 = 0xC0C 68 val Hpmcounter13 = 0xC0D 69 val Hpmcounter14 = 0xC0E 70 val Hpmcounter15 = 0xC0F 71 val Hpmcounter16 = 0xC10 72 val Hpmcounter17 = 0xC11 73 val Hpmcounter18 = 0xC12 74 val Hpmcounter19 = 0xC13 75 val Hpmcounter20 = 0xC14 76 val Hpmcounter21 = 0xC15 77 val Hpmcounter22 = 0xC16 78 val Hpmcounter23 = 0xC17 79 val Hpmcounter24 = 0xC18 80 val Hpmcounter25 = 0xC19 81 val Hpmcounter26 = 0xC1A 82 val Hpmcounter27 = 0xC1B 83 val Hpmcounter28 = 0xC1C 84 val Hpmcounter29 = 0xC1D 85 val Hpmcounter30 = 0xC1E 86 val Hpmcounter31 = 0xC1F 87 88 // Supervisor Trap Setup 89 val Sstatus = 0x100 90 val Sedeleg = 0x102 91 val Sideleg = 0x103 92 val Sie = 0x104 93 val Stvec = 0x105 94 val Scounteren = 0x106 95 96 // Supervisor Configuration 97 val Senvcfg = 0x10A 98 99 // Supervisor Trap Handling 100 val Sscratch = 0x140 101 val Sepc = 0x141 102 val Scause = 0x142 103 val Stval = 0x143 104 val Sip = 0x144 105 106 // Supervisor Protection and Translation 107 val Satp = 0x180 108 109 // Supervisor Custom Read/Write 110 val Sbpctl = 0x5C0 111 val Spfctl = 0x5C1 112 val Slvpredctl = 0x5C2 113 val Smblockctl = 0x5C3 114 val Srnctl = 0x5C4 115 /** 0x5C5-0x5E5 for cache instruction register*/ 116 val Scachebase = 0x5C5 117 118 // Supervisor Custom Read/Write 119 val Sdsid = 0x9C0 120 val Sfetchctl = 0x9e0 121 122 // Machine Information Registers 123 val Mvendorid = 0xF11 124 val Marchid = 0xF12 125 val Mimpid = 0xF13 126 val Mhartid = 0xF14 127 val Mconfigptr = 0xF15 128 129 // Machine Trap Setup 130 val Mstatus = 0x300 131 val Misa = 0x301 132 val Medeleg = 0x302 133 val Mideleg = 0x303 134 val Mie = 0x304 135 val Mtvec = 0x305 136 val Mcounteren = 0x306 137 138 // Machine Trap Handling 139 val Mscratch = 0x340 140 val Mepc = 0x341 141 val Mcause = 0x342 142 val Mtval = 0x343 143 val Mip = 0x344 144 145 // Machine Configuration 146 val Menvcfg = 0x30A 147 148 // Machine Memory Protection 149 // TBD 150 val PmpcfgBase = 0x3A0 151 val PmpaddrBase = 0x3B0 152 // Machine level PMA 153 val PmacfgBase = 0x7C0 154 val PmaaddrBase = 0x7C8 // 64 entry at most 155 156 // Machine Counter/Timers 157 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 158 // 0xB80 - 0x89F are also used as perfcnt csr 159 val Mcycle = 0xb00 160 val Minstret = 0xb02 161 162 val Mhpmcounter3 = 0xB03 163 val Mhpmcounter4 = 0xB04 164 val Mhpmcounter5 = 0xB05 165 val Mhpmcounter6 = 0xB06 166 val Mhpmcounter7 = 0xB07 167 val Mhpmcounter8 = 0xB08 168 val Mhpmcounter9 = 0xB09 169 val Mhpmcounter10 = 0xB0A 170 val Mhpmcounter11 = 0xB0B 171 val Mhpmcounter12 = 0xB0C 172 val Mhpmcounter13 = 0xB0D 173 val Mhpmcounter14 = 0xB0E 174 val Mhpmcounter15 = 0xB0F 175 val Mhpmcounter16 = 0xB10 176 val Mhpmcounter17 = 0xB11 177 val Mhpmcounter18 = 0xB12 178 val Mhpmcounter19 = 0xB13 179 val Mhpmcounter20 = 0xB14 180 val Mhpmcounter21 = 0xB15 181 val Mhpmcounter22 = 0xB16 182 val Mhpmcounter23 = 0xB17 183 val Mhpmcounter24 = 0xB18 184 val Mhpmcounter25 = 0xB19 185 val Mhpmcounter26 = 0xB1A 186 val Mhpmcounter27 = 0xB1B 187 val Mhpmcounter28 = 0xB1C 188 val Mhpmcounter29 = 0xB1D 189 val Mhpmcounter30 = 0xB1E 190 val Mhpmcounter31 = 0xB1F 191 192 val Mcountinhibit = 0x320 193 val Mhpmevent3 = 0x323 194 val Mhpmevent4 = 0x324 195 val Mhpmevent5 = 0x325 196 val Mhpmevent6 = 0x326 197 val Mhpmevent7 = 0x327 198 val Mhpmevent8 = 0x328 199 val Mhpmevent9 = 0x329 200 val Mhpmevent10 = 0x32A 201 val Mhpmevent11 = 0x32B 202 val Mhpmevent12 = 0x32C 203 val Mhpmevent13 = 0x32D 204 val Mhpmevent14 = 0x32E 205 val Mhpmevent15 = 0x32F 206 val Mhpmevent16 = 0x330 207 val Mhpmevent17 = 0x331 208 val Mhpmevent18 = 0x332 209 val Mhpmevent19 = 0x333 210 val Mhpmevent20 = 0x334 211 val Mhpmevent21 = 0x335 212 val Mhpmevent22 = 0x336 213 val Mhpmevent23 = 0x337 214 val Mhpmevent24 = 0x338 215 val Mhpmevent25 = 0x339 216 val Mhpmevent26 = 0x33A 217 val Mhpmevent27 = 0x33B 218 val Mhpmevent28 = 0x33C 219 val Mhpmevent29 = 0x33D 220 val Mhpmevent30 = 0x33E 221 val Mhpmevent31 = 0x33F 222 223 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 224 225 // Trigger Registers 226 val Tselect = 0x7A0 227 val Tdata1 = 0x7A1 228 val Tdata2 = 0x7A2 229 val Tinfo = 0x7A4 230 val Tcontrol = 0x7A5 231 232 // Debug Mode Registers 233 val Dcsr = 0x7B0 234 val Dpc = 0x7B1 235 val Dscratch0 = 0x7B2 236 val Dscratch1 = 0x7B3 237 238 def privEcall = 0x000.U 239 def privEbreak = 0x001.U 240 def privMret = 0x302.U 241 def privSret = 0x102.U 242 def privUret = 0x002.U 243 def privDret = 0x7b2.U 244 245 def ModeM = 0x3.U 246 def ModeH = 0x2.U 247 def ModeS = 0x1.U 248 def ModeU = 0x0.U 249 250 def IRQ_USIP = 0 251 def IRQ_SSIP = 1 252 def IRQ_MSIP = 3 253 254 def IRQ_UTIP = 4 255 def IRQ_STIP = 5 256 def IRQ_MTIP = 7 257 258 def IRQ_UEIP = 8 259 def IRQ_SEIP = 9 260 def IRQ_MEIP = 11 261 262 def IRQ_DEBUG = 12 263 264 val Satp_Mode_len = 4 265 val Satp_Asid_len = 16 266 val Satp_Addr_len = 44 267 def satp_part_wmask(max_length: Int, length: Int) : UInt = { 268 require(length > 0 && length <= max_length) 269 ((1L << length) - 1).U(max_length.W) 270 } 271 272 val IntPriority = Seq( 273 IRQ_DEBUG, 274 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 275 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 276 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 277 ) 278 279 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 280 val readOnly = addr(11,10) === "b11".U 281 val lowestAccessPrivilegeLevel = addr(9,8) 282 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 283 } 284 285 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 286 val index = UIntToOH(addr & 31.U) 287 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 288 } 289 290 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 291 // debug mode write only regs 292 val isDebugReg = addr(11, 4) === "h7b".U 293 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 294 } 295 296 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 297 val isTriggerReg = addr(11, 4) === "h7a".U 298 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 299 } 300} 301object CSRConst extends HasCSRConst