1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.util 18 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import xiangshan._ 23import xiangshan.backend._ 24import utils.XSDebug 25 26trait HasCSRConst { 27 28 // User Trap Setup 29 val Ustatus = 0x000 30 val Uie = 0x004 31 val Utvec = 0x005 32 33 // User Trap Handling 34 val Uscratch = 0x040 35 val Uepc = 0x041 36 val Ucause = 0x042 37 val Utval = 0x043 38 val Uip = 0x044 39 40 // User Floating-Point CSRs (not implemented) 41 val Fflags = 0x001 42 val Frm = 0x002 43 val Fcsr = 0x003 44 45 // Vector Extension CSRs 46 val Vstart = 0x008 47 val Vxsat = 0x009 48 val Vxrm = 0x00A 49 val Vcsr = 0x00F 50 val Vl = 0xC20 51 val Vtype = 0xC21 52 val Vlenb = 0xC22 53 54 // User Counter/Timers 55 val Cycle = 0xC00 56 val Time = 0xC01 57 val Instret = 0xC02 58 59 // Supervisor Trap Setup 60 val Sstatus = 0x100 61 val Sedeleg = 0x102 62 val Sideleg = 0x103 63 val Sie = 0x104 64 val Stvec = 0x105 65 val Scounteren = 0x106 66 67 // Supervisor Trap Handling 68 val Sscratch = 0x140 69 val Sepc = 0x141 70 val Scause = 0x142 71 val Stval = 0x143 72 val Sip = 0x144 73 74 // Supervisor Protection and Translation 75 val Satp = 0x180 76 77 // Supervisor Custom Read/Write 78 val Sbpctl = 0x5C0 79 val Spfctl = 0x5C1 80 val Slvpredctl = 0x5C2 81 val Smblockctl = 0x5C3 82 val Srnctl = 0x5C4 83 val Scachebase = 0x5C5 84 val Sfetchctl = 0x5C6 85 86 /** 0x5C5-0x5E5 for cache instruction register*/ 87 88 val Sdsid = 0x9C0 89 90 // Machine Information Registers 91 val Mvendorid = 0xF11 92 val Marchid = 0xF12 93 val Mimpid = 0xF13 94 val Mhartid = 0xF14 95 val Mconfigptr = 0xF15 96 97 // Machine Trap Setup 98 val Mstatus = 0x300 99 val Misa = 0x301 100 val Medeleg = 0x302 101 val Mideleg = 0x303 102 val Mie = 0x304 103 val Mtvec = 0x305 104 val Mcounteren = 0x306 105 106 // Machine Trap Handling 107 val Mscratch = 0x340 108 val Mepc = 0x341 109 val Mcause = 0x342 110 val Mtval = 0x343 111 val Mip = 0x344 112 113 // Machine Memory Protection 114 // TBD 115 val PmpcfgBase = 0x3A0 116 val PmpaddrBase = 0x3B0 117 // Machine level PMA 118 val PmacfgBase = 0x7C0 119 val PmaaddrBase = 0x7C8 // 64 entry at most 120 121 // Machine Counter/Timers 122 // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers 123 // 0xB80 - 0x89F are also used as perfcnt csr 124 val Mcycle = 0xb00 125 val Minstret = 0xb02 126 127 val Mhpmcounter3 = 0xB03 128 val Mhpmcounter4 = 0xB04 129 val Mhpmcounter5 = 0xB05 130 val Mhpmcounter6 = 0xB06 131 val Mhpmcounter7 = 0xB07 132 val Mhpmcounter8 = 0xB08 133 val Mhpmcounter9 = 0xB09 134 val Mhpmcounter10 = 0xB0A 135 val Mhpmcounter11 = 0xB0B 136 val Mhpmcounter12 = 0xB0C 137 val Mhpmcounter13 = 0xB0D 138 val Mhpmcounter14 = 0xB0E 139 val Mhpmcounter15 = 0xB0F 140 val Mhpmcounter16 = 0xB10 141 val Mhpmcounter17 = 0xB11 142 val Mhpmcounter18 = 0xB12 143 val Mhpmcounter19 = 0xB13 144 val Mhpmcounter20 = 0xB14 145 val Mhpmcounter21 = 0xB15 146 val Mhpmcounter22 = 0xB16 147 val Mhpmcounter23 = 0xB17 148 val Mhpmcounter24 = 0xB18 149 val Mhpmcounter25 = 0xB19 150 val Mhpmcounter26 = 0xB1A 151 val Mhpmcounter27 = 0xB1B 152 val Mhpmcounter28 = 0xB1C 153 val Mhpmcounter29 = 0xB1D 154 val Mhpmcounter30 = 0xB1E 155 val Mhpmcounter31 = 0xB1F 156 157 val Mcountinhibit = 0x320 158 val Mhpmevent3 = 0x323 159 val Mhpmevent4 = 0x324 160 val Mhpmevent5 = 0x325 161 val Mhpmevent6 = 0x326 162 val Mhpmevent7 = 0x327 163 val Mhpmevent8 = 0x328 164 val Mhpmevent9 = 0x329 165 val Mhpmevent10 = 0x32A 166 val Mhpmevent11 = 0x32B 167 val Mhpmevent12 = 0x32C 168 val Mhpmevent13 = 0x32D 169 val Mhpmevent14 = 0x32E 170 val Mhpmevent15 = 0x32F 171 val Mhpmevent16 = 0x330 172 val Mhpmevent17 = 0x331 173 val Mhpmevent18 = 0x332 174 val Mhpmevent19 = 0x333 175 val Mhpmevent20 = 0x334 176 val Mhpmevent21 = 0x335 177 val Mhpmevent22 = 0x336 178 val Mhpmevent23 = 0x337 179 val Mhpmevent24 = 0x338 180 val Mhpmevent25 = 0x339 181 val Mhpmevent26 = 0x33A 182 val Mhpmevent27 = 0x33B 183 val Mhpmevent28 = 0x33C 184 val Mhpmevent29 = 0x33D 185 val Mhpmevent30 = 0x33E 186 val Mhpmevent31 = 0x33F 187 188 // Debug/Trace Registers (shared with Debug Mode) (not implemented) 189 190 // Trigger Registers 191 val Tselect = 0x7A0 192 val Tdata1 = 0x7A1 193 val Tdata2 = 0x7A2 194 val Tinfo = 0x7A4 195 val Tcontrol = 0x7A5 196 197 // Debug Mode Registers 198 val Dcsr = 0x7B0 199 val Dpc = 0x7B1 200 val Dscratch = 0x7B2 201 val Dscratch1 = 0x7B3 202 203 def privEcall = 0x000.U 204 def privEbreak = 0x001.U 205 def privMret = 0x302.U 206 def privSret = 0x102.U 207 def privUret = 0x002.U 208 def privDret = 0x7b2.U 209 210 def ModeM = 0x3.U 211 def ModeH = 0x2.U 212 def ModeS = 0x1.U 213 def ModeU = 0x0.U 214 215 def IRQ_UEIP = 0 216 def IRQ_SEIP = 1 217 def IRQ_MEIP = 3 218 219 def IRQ_UTIP = 4 220 def IRQ_STIP = 5 221 def IRQ_MTIP = 7 222 223 def IRQ_USIP = 8 224 def IRQ_SSIP = 9 225 def IRQ_MSIP = 11 226 227 def IRQ_DEBUG = 12 228 229 val Satp_Mode_len = 4 230 val Satp_Asid_len = 16 231 val Satp_Addr_len = 44 232 def satp_part_wmask(max_length: Int, length: Int) : UInt = { 233 require(length > 0 && length <= max_length) 234 ((1L << length) - 1).U(max_length.W) 235 } 236 237 val IntPriority = Seq( 238 IRQ_DEBUG, 239 IRQ_MEIP, IRQ_MSIP, IRQ_MTIP, 240 IRQ_SEIP, IRQ_SSIP, IRQ_STIP, 241 IRQ_UEIP, IRQ_USIP, IRQ_UTIP 242 ) 243 244 def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = { 245 val readOnly = addr(11,10) === "b11".U 246 val lowestAccessPrivilegeLevel = addr(9,8) 247 mode >= lowestAccessPrivilegeLevel && !(wen && readOnly) 248 } 249 250 def perfcntPermissionCheck(addr: UInt, mode: UInt, mmask: UInt, smask: UInt): Bool = { 251 val index = UIntToOH(addr & 31.U) 252 Mux(mode === ModeM, true.B, Mux(mode === ModeS, (index & mmask) =/= 0.U, (index & mmask & smask) =/= 0.U)) 253 } 254 255 def dcsrPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 256 // debug mode write only regs 257 val isDebugReg = addr(11, 4) === "h7b".U 258 Mux(!mModeCanWrite && isDebugReg, debug, true.B) 259 } 260 261 def triggerPermissionCheck(addr: UInt, mModeCanWrite: UInt, debug: Bool): Bool = { 262 val isTriggerReg = addr(11, 4) === "h7a".U 263 Mux(!mModeCanWrite && isTriggerReg, debug, true.B) 264 } 265} 266