1// See LICENSE.Berkeley for license details. 2// See LICENSE.SiFive for license details. 3 4package xiangshan.backend.fu.fpu 5 6import chisel3._ 7import hardfloat.INToRecFN 8import utils.{SignExt, ZeroExt} 9 10class IntToFP extends FPUSubModule { 11 12 val ctrl = io.in.bits.uop.ctrl.fpu 13 val tag = ctrl.typeTagIn 14 val typ = ctrl.typ 15 val wflags = ctrl.wflags 16 val src1 = io.in.bits.src(0)(XLEN-1, 0) 17 18 val mux = Wire(new Bundle() { 19 val data = UInt((XLEN+1).W) 20 val exc = UInt(5.W) 21 }) 22 mux.data := recode(src1, tag) 23 mux.exc := 0.U 24 25 val intValue = Mux(typ(1), 26 Mux(typ(0), ZeroExt(src1, XLEN), SignExt(src1, XLEN)), 27 Mux(typ(0), ZeroExt(src1(31, 0), XLEN), SignExt(src1(31, 0), XLEN)) 28 ) 29 30 when(wflags){ 31 val i2fResults = for(t <- floatTypes) yield { 32 val i2f = Module(new INToRecFN(XLEN, t.exp, t.sig)) 33 i2f.io.signedIn := ~typ(0) 34 i2f.io.in := intValue 35 i2f.io.roundingMode := rm 36 i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding 37 (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) 38 } 39 val (data, exc) = i2fResults.unzip 40 mux.data := VecInit(data)(tag) 41 mux.exc := VecInit(exc)(tag) 42 } 43 44 fflags := mux.exc 45 io.out.bits.uop := io.in.bits.uop 46 io.out.bits.data := box(mux.data, io.in.bits.uop.ctrl.fpu.typeTagOut) 47 io.out.valid := io.in.valid 48 io.in.ready := io.out.ready 49} 50