1package xiangshan.backend.fu.fpu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7import xiangshan.backend.fu.{FuConfig, FuncUnit, HasPipelineReg} 8 9trait FpFuncUnitAlias { this: FuncUnit => 10 protected val inCtrl = io.in.bits.ctrl 11 protected val inData = io.in.bits.data 12 protected val fpCtrl = inCtrl.vpu.get 13 protected val fp_fmt = fpCtrl.vsew // TODO: use fpu 14 15 protected val frm = io.frm.getOrElse(0.U(3.W)) 16 protected val instRm = inCtrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).rm 17 protected val rm = Mux(instRm =/= "b111".U, instRm, frm) 18 19 protected val fuOpType = inCtrl.fuOpType 20} 21 22class FpPipedFuncUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 23 with HasPipelineReg 24 with FpFuncUnitAlias 25{ 26 protected val outCtrl = ctrlVec.last 27 protected val outData = dataVec.last 28 29 override def latency: Int = cfg.latency.latencyVal.get 30 31} 32