1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu.fpu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.{FPUCtrlSignals, XSModule} 23import xiangshan.backend.fu.{FunctionUnit, HasPipelineReg} 24 25trait HasUIntToSIntHelper { 26 implicit class UIntToSIntHelper(x: UInt){ 27 def toSInt: SInt = Cat(0.U(1.W), x).asSInt() 28 } 29} 30 31abstract class FPUDataModule(implicit p: Parameters) extends XSModule { 32 val io = IO(new Bundle() { 33 val in = Input(new Bundle() { 34 val src = Vec(3, UInt(64.W)) 35 val fpCtrl = new FPUCtrlSignals 36 val rm = UInt(3.W) 37 }) 38 val out = Output(new Bundle() { 39 val data = UInt(64.W) 40 val fflags = UInt(5.W) 41 }) 42 }) 43 44 val rm = io.in.rm 45 val fflags = io.out.fflags 46} 47 48abstract class FPUSubModule(implicit p: Parameters) extends FunctionUnit 49 with HasUIntToSIntHelper 50{ 51 val rm = IO(Input(UInt(3.W))) 52 val fflags = IO(Output(UInt(5.W))) 53 val dataModule: FPUDataModule 54 def connectDataModule = { 55 dataModule.io.in.src <> io.in.bits.src 56 dataModule.io.in.fpCtrl <> io.in.bits.uop.ctrl.fpu 57 dataModule.io.in.rm <> rm 58 io.out.bits.data := dataModule.io.out.data 59 fflags := dataModule.io.out.fflags 60 } 61 def invert_sign(x: UInt, len: Int) = { 62 Cat( 63 !x(len-1), x(len-2, 0) 64 ) 65 } 66} 67 68abstract class FPUPipelineModule(implicit p: Parameters) 69 extends FPUSubModule 70 with HasPipelineReg 71