1package xiangshan.backend.fu.fpu 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan.{FPUCtrlSignals, XSModule} 6import xiangshan.backend.fu.{FuConfig, FunctionUnit, HasPipelineReg} 7 8trait HasUIntToSIntHelper { 9 implicit class UIntToSIntHelper(x: UInt){ 10 def toSInt: SInt = Cat(0.U(1.W), x).asSInt() 11 } 12} 13 14abstract class FPUDataModule extends XSModule { 15 val io = IO(new Bundle() { 16 val in = Input(new Bundle() { 17 val src = Vec(3, UInt(65.W)) 18 val fpCtrl = new FPUCtrlSignals 19 val rm = UInt(3.W) 20 }) 21 val out = Output(new Bundle() { 22 val data = UInt(65.W) 23 val fflags = UInt(5.W) 24 }) 25 }) 26 27 val rm = io.in.rm 28 val fflags = io.out.fflags 29} 30 31abstract class FPUSubModule extends FunctionUnit(len = 65) 32 with HasUIntToSIntHelper 33{ 34 val rm = IO(Input(UInt(3.W))) 35 val fflags = IO(Output(UInt(5.W))) 36 val dataModule: FPUDataModule 37 def connectDataModule = { 38 dataModule.io.in.src <> io.in.bits.src 39 dataModule.io.in.fpCtrl <> io.in.bits.uop.ctrl.fpu 40 dataModule.io.in.rm <> rm 41 io.out.bits.data := dataModule.io.out.data 42 fflags := dataModule.io.out.fflags 43 } 44} 45 46abstract class FPUPipelineModule 47 extends FPUSubModule 48 with HasPipelineReg