xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala (revision f062e05dd530061d36b70120910d6311c5ad2a58) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import utility.ParallelMux
24
25class VsetModule(implicit p: Parameters) extends XSModule {
26  val io = IO(new Bundle() {
27    val lsrc0NotZero = Input(Bool())
28    val ldest = Input(UInt(6.W))
29    val src0  = Input(UInt(XLEN.W))
30    val src1  = Input(UInt(XLEN.W))
31    val func  = Input(FuOpType())
32    val vconfig = Input(UInt(16.W))
33
34    val res   = Output(UInt(XLEN.W))
35  })
36
37  val vtype = io.src1(7, 0)
38  val vlmul = vtype(2, 0)
39  val vsew = vtype(5, 3)
40
41  val avlImm = Cat(0.U(3.W), io.src1(14, 10))
42  val vlLast = io.vconfig(15, 8)
43
44  val rd = io.ldest
45  val lsrc0NotZero = io.lsrc0NotZero
46  val vl = WireInit(0.U(XLEN.W))
47  val vconfig = WireInit(0.U(XLEN.W))
48
49  // vlen =  128
50  val vlmaxVec = (0 to 7).map(i => if(i < 4) (16 << i).U(8.W) else (16 >> (8 - i)).U(8.W))
51  val shamt = vlmul + (~vsew).asUInt + 1.U
52  val vlmax = ParallelMux((0 to 7).map(_.U).map(_ === shamt), vlmaxVec)
53
54  val isVsetivli = io.func === ALUOpType.vsetivli2 || io.func === ALUOpType.vsetivli1
55  val vlWhenRs1Not0 = Mux(isVsetivli, Mux(avlImm > vlmax, vlmax, avlImm),
56                                      Mux(io.src0 > vlmax, vlmax, io.src0))
57  vl := Mux(isVsetivli, Mux(avlImm > vlmax, vlmax, avlImm),
58        Mux(lsrc0NotZero, Mux(io.src0 > vlmax, vlmax, io.src0),
59        Mux(rd === 0.U, Cat(0.U(56.W), vlLast), vlmax)))
60
61  vconfig := Cat(0.U(48.W), vl(7, 0), vtype)
62
63  io.res := Mux(io.func === ALUOpType.vsetvli2 || io.func === ALUOpType.vsetvl2 || io.func === ALUOpType.vsetivli2, vl, vconfig)
64}
65
66class Vset(implicit p: Parameters) extends FUWithRedirect {
67
68  val uop = io.in.bits.uop
69
70  // vset
71
72  val isVset = ALUOpType.isVset(io.in.bits.uop.ctrl.fuOpType)
73  val dataModule = Module(new VsetModule)
74
75  dataModule.io.lsrc0NotZero := uop.ctrl.imm(15) // lsrc(0) Not Zero
76  dataModule.io.ldest := uop.ctrl.ldest
77  dataModule.io.src0 := io.in.bits.src(0)
78  dataModule.io.src1 := io.in.bits.src(1)
79  dataModule.io.func := io.in.bits.uop.ctrl.fuOpType
80  dataModule.io.vconfig := uop.ctrl.vconfig
81
82  redirectOutValid := false.B
83  redirectOut := DontCare
84
85  io.in.ready := io.out.ready
86  io.out.valid := io.in.valid && isVset
87  io.out.bits.uop <> io.in.bits.uop
88  io.out.bits.data := dataModule.io.res
89}