1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17// See LICENSE.SiFive for license details. 18 19package xiangshan.backend.fu 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3._ 23import chisel3.internal.naming.chiselName 24import chisel3.util._ 25import utils.MaskedRegMap.WritableMask 26import xiangshan._ 27import xiangshan.backend.fu.util.HasCSRConst 28import utils._ 29import xiangshan.cache.mmu.{TlbCmd, TlbExceptionBundle} 30 31trait PMPConst extends HasPMParameters { 32 val PMPOffBits = 2 // minimal 4bytes 33 val CoarserGrain: Boolean = PlatformGrain > PMPOffBits 34} 35 36abstract class PMPBundle(implicit val p: Parameters) extends Bundle with PMPConst 37abstract class PMPModule(implicit val p: Parameters) extends Module with PMPConst 38abstract class PMPXSModule(implicit p: Parameters) extends XSModule with PMPConst 39 40@chiselName 41class PMPConfig(implicit p: Parameters) extends PMPBundle { 42 val l = Bool() 43 val c = Bool() // res(1), unuse in pmp 44 val atomic = Bool() // res(0), unuse in pmp 45 val a = UInt(2.W) 46 val x = Bool() 47 val w = Bool() 48 val r = Bool() 49 50 def res: UInt = Cat(c, atomic) // in pmp, unused 51 def off = a === 0.U 52 def tor = a === 1.U 53 def na4 = { if (CoarserGrain) false.B else a === 2.U } 54 def napot = { if (CoarserGrain) a(1).asBool else a === 3.U } 55 def off_tor = !a(1) 56 def na4_napot = a(1) 57 58 def locked = l 59 def addr_locked: Bool = locked 60 def addr_locked(next: PMPConfig): Bool = locked || (next.locked && next.tor) 61} 62 63trait PMPReadWriteMethodBare extends PMPConst { 64 def match_mask(cfg: PMPConfig, paddr: UInt) = { 65 val match_mask_c_addr = Cat(paddr, cfg.a(0)) | (((1 << PlatformGrain) - 1) >> PMPOffBits).U((paddr.getWidth + 1).W) 66 Cat(match_mask_c_addr & ~(match_mask_c_addr + 1.U), ((1 << PMPOffBits) - 1).U(PMPOffBits.W)) 67 } 68 69 def write_cfg_vec(mask: Vec[UInt], addr: Vec[UInt], index: Int)(cfgs: UInt): UInt = { 70 val cfgVec = Wire(Vec(cfgs.getWidth/8, new PMPConfig)) 71 for (i <- cfgVec.indices) { 72 val cfg_w_m_tmp = cfgs((i+1)*8-1, i*8).asUInt.asTypeOf(new PMPConfig) 73 cfgVec(i) := cfg_w_m_tmp 74 cfgVec(i).w := cfg_w_m_tmp.w && cfg_w_m_tmp.r 75 if (CoarserGrain) { cfgVec(i).a := Cat(cfg_w_m_tmp.a(1), cfg_w_m_tmp.a.orR) } 76 when (cfgVec(i).na4_napot) { 77 mask(index + i) := match_mask(cfgVec(i), addr(index + i)) 78 } 79 } 80 cfgVec.asUInt 81 } 82 83 def read_addr(cfg: PMPConfig)(addr: UInt): UInt = { 84 val G = PlatformGrain - PMPOffBits 85 require(G >= 0) 86 if (G == 0) { 87 addr 88 } else if (G >= 2) { 89 Mux(cfg.na4_napot, set_low_bits(addr, G-1), clear_low_bits(addr, G)) 90 } else { // G is 1 91 Mux(cfg.off_tor, clear_low_bits(addr, G), addr) 92 } 93 } 94 95 def write_addr(next: PMPConfig, mask: UInt)(paddr: UInt, cfg: PMPConfig, addr: UInt): UInt = { 96 val locked = cfg.addr_locked(next) 97 mask := Mux(!locked, match_mask(cfg, paddr), mask) 98 Mux(!locked, paddr, addr) 99 } 100 101 def set_low_bits(data: UInt, num: Int): UInt = { 102 require(num >= 0) 103 data | ((1 << num)-1).U 104 } 105 106 /** mask the data's low num bits (lsb) */ 107 def clear_low_bits(data: UInt, num: Int): UInt = { 108 require(num >= 0) 109 // use Cat instead of & with mask to avoid "Signal Width" problem 110 if (num == 0) { data } 111 else { Cat(data(data.getWidth-1, num), 0.U(num.W)) } 112 } 113} 114 115trait PMPReadWriteMethod extends PMPReadWriteMethodBare { this: PMPBase => 116 def write_cfg_vec(cfgs: UInt): UInt = { 117 val cfgVec = Wire(Vec(cfgs.getWidth/8, new PMPConfig)) 118 for (i <- cfgVec.indices) { 119 val cfg_w_tmp = cfgs((i+1)*8-1, i*8).asUInt.asTypeOf(new PMPConfig) 120 cfgVec(i) := cfg_w_tmp 121 cfgVec(i).w := cfg_w_tmp.w && cfg_w_tmp.r 122 if (CoarserGrain) { cfgVec(i).a := Cat(cfg_w_tmp.a(1), cfg_w_tmp.a.orR) } 123 } 124 cfgVec.asUInt 125 } 126 127 /** In general, the PMP grain is 2**{G+2} bytes. when G >= 1, na4 is not selectable. 128 * When G >= 2 and cfg.a(1) is set(then the mode is napot), the bits addr(G-2, 0) read as zeros. 129 * When G >= 1 and cfg.a(1) is clear(the mode is off or tor), the addr(G-1, 0) read as zeros. 130 * The low OffBits is dropped 131 */ 132 def read_addr(): UInt = { 133 read_addr(cfg)(addr) 134 } 135 136 /** addr for inside addr, drop OffBits with. 137 * compare_addr for inside addr for comparing. 138 * paddr for outside addr. 139 */ 140 def write_addr(next: PMPConfig)(paddr: UInt): UInt = { 141 Mux(!cfg.addr_locked(next), paddr, addr) 142 } 143 def write_addr(paddr: UInt): UInt = { 144 Mux(!cfg.addr_locked, paddr, addr) 145 } 146} 147 148/** PMPBase for CSR unit 149 * with only read and write logic 150 */ 151@chiselName 152class PMPBase(implicit p: Parameters) extends PMPBundle with PMPReadWriteMethod { 153 val cfg = new PMPConfig 154 val addr = UInt((PMPAddrBits - PMPOffBits).W) 155 156 def gen(cfg: PMPConfig, addr: UInt) = { 157 require(addr.getWidth == this.addr.getWidth) 158 this.cfg := cfg 159 this.addr := addr 160 } 161} 162 163trait PMPMatchMethod extends PMPConst { this: PMPEntry => 164 /** compare_addr is used to compare with input addr */ 165 def compare_addr: UInt = ((addr << PMPOffBits) & ~(((1 << PlatformGrain) - 1).U(PMPAddrBits.W))).asUInt 166 167 /** size and maxSize are all log2 Size 168 * for dtlb, the maxSize is bPMXLEN which is 8 169 * for itlb and ptw, the maxSize is log2(512) ? 170 * but we may only need the 64 bytes? how to prevent the bugs? 171 * TODO: handle the special case that itlb & ptw & dcache access wider size than PMXLEN 172 */ 173 def is_match(paddr: UInt, lgSize: UInt, lgMaxSize: Int, last_pmp: PMPEntry): Bool = { 174 Mux(cfg.na4_napot, napotMatch(paddr, lgSize, lgMaxSize), 175 Mux(cfg.tor, torMatch(paddr, lgSize, lgMaxSize, last_pmp), false.B)) 176 } 177 178 /** generate match mask to help match in napot mode */ 179 def match_mask(paddr: UInt): UInt = { 180 match_mask(cfg, paddr) 181 } 182 183 def boundMatch(paddr: UInt, lgSize: UInt, lgMaxSize: Int): Bool = { 184 if (lgMaxSize <= PlatformGrain) { 185 (paddr < compare_addr) 186 } else { 187 val highLess = (paddr >> lgMaxSize) < (compare_addr >> lgMaxSize) 188 val highEqual = (paddr >> lgMaxSize) === (compare_addr >> lgMaxSize) 189 val lowLess = (paddr(lgMaxSize-1, 0) | OneHot.UIntToOH1(lgSize, lgMaxSize)) < compare_addr(lgMaxSize-1, 0) 190 highLess || (highEqual && lowLess) 191 } 192 } 193 194 def lowerBoundMatch(paddr: UInt, lgSize: UInt, lgMaxSize: Int): Bool = { 195 !boundMatch(paddr, lgSize, lgMaxSize) 196 } 197 198 def higherBoundMatch(paddr: UInt, lgMaxSize: Int) = { 199 boundMatch(paddr, 0.U, lgMaxSize) 200 } 201 202 def torMatch(paddr: UInt, lgSize: UInt, lgMaxSize: Int, last_pmp: PMPEntry): Bool = { 203 last_pmp.lowerBoundMatch(paddr, lgSize, lgMaxSize) && higherBoundMatch(paddr, lgMaxSize) 204 } 205 206 def unmaskEqual(a: UInt, b: UInt, m: UInt) = { 207 (a & ~m) === (b & ~m) 208 } 209 210 def napotMatch(paddr: UInt, lgSize: UInt, lgMaxSize: Int) = { 211 if (lgMaxSize <= PlatformGrain) { 212 unmaskEqual(paddr, compare_addr, mask) 213 } else { 214 val lowMask = mask | OneHot.UIntToOH1(lgSize, lgMaxSize) 215 val highMatch = unmaskEqual(paddr >> lgMaxSize, compare_addr >> lgMaxSize, mask >> lgMaxSize) 216 val lowMatch = unmaskEqual(paddr(lgMaxSize-1, 0), compare_addr(lgMaxSize-1, 0), lowMask(lgMaxSize-1, 0)) 217 highMatch && lowMatch 218 } 219 } 220 221 def aligned(paddr: UInt, lgSize: UInt, lgMaxSize: Int, last: PMPEntry) = { 222 if (lgMaxSize <= PlatformGrain) { 223 true.B 224 } else { 225 val lowBitsMask = OneHot.UIntToOH1(lgSize, lgMaxSize) 226 val lowerBound = ((paddr >> lgMaxSize) === (last.compare_addr >> lgMaxSize)) && 227 ((~paddr(lgMaxSize-1, 0) & last.compare_addr(lgMaxSize-1, 0)) =/= 0.U) 228 val upperBound = ((paddr >> lgMaxSize) === (compare_addr >> lgMaxSize)) && 229 ((compare_addr(lgMaxSize-1, 0) & (paddr(lgMaxSize-1, 0) | lowBitsMask)) =/= 0.U) 230 val torAligned = !(lowerBound || upperBound) 231 val napotAligned = (lowBitsMask & ~mask(lgMaxSize-1, 0)) === 0.U 232 Mux(cfg.na4_napot, napotAligned, torAligned) 233 } 234 } 235} 236 237/** PMPEntry for outside pmp copies 238 * with one more elements mask to help napot match 239 * TODO: make mask an element, not an method, for timing opt 240 */ 241@chiselName 242class PMPEntry(implicit p: Parameters) extends PMPBase with PMPMatchMethod { 243 val mask = UInt(PMPAddrBits.W) // help to match in napot 244 245 def write_addr(next: PMPConfig, mask: UInt)(paddr: UInt) = { 246 mask := Mux(!cfg.addr_locked(next), match_mask(paddr), mask) 247 Mux(!cfg.addr_locked(next), paddr, addr) 248 } 249 250 def write_addr(mask: UInt)(paddr: UInt) = { 251 mask := Mux(!cfg.addr_locked, match_mask(paddr), mask) 252 Mux(!cfg.addr_locked, paddr, addr) 253 } 254 255 def gen(cfg: PMPConfig, addr: UInt, mask: UInt) = { 256 require(addr.getWidth == this.addr.getWidth) 257 this.cfg := cfg 258 this.addr := addr 259 this.mask := mask 260 } 261} 262 263trait PMPMethod extends PMPConst { 264 def pmp_init() : (Vec[UInt], Vec[UInt], Vec[UInt])= { 265 val cfg = WireInit(0.U.asTypeOf(Vec(NumPMP/8, UInt(PMXLEN.W)))) 266 val addr = Wire(Vec(NumPMP, UInt((PMPAddrBits-PMPOffBits).W))) 267 val mask = Wire(Vec(NumPMP, UInt(PMPAddrBits.W))) 268 addr := DontCare 269 mask := DontCare 270 (cfg, addr, mask) 271 } 272 273 def pmp_gen_mapping 274 ( 275 init: () => (Vec[UInt], Vec[UInt], Vec[UInt]), 276 num: Int = 16, 277 cfgBase: Int, 278 addrBase: Int, 279 entries: Vec[PMPEntry] 280 ) = { 281 val pmpCfgPerCSR = PMXLEN / new PMPConfig().getWidth 282 def pmpCfgIndex(i: Int) = (PMXLEN / 32) * (i / pmpCfgPerCSR) 283 val init_value = init() 284 /** to fit MaskedRegMap's write, declare cfgs as Merged CSRs and split them into each pmp */ 285 val cfgMerged = RegInit(init_value._1) //(Vec(num / pmpCfgPerCSR, UInt(PMXLEN.W))) // RegInit(VecInit(Seq.fill(num / pmpCfgPerCSR)(0.U(PMXLEN.W)))) 286 val cfgs = WireInit(cfgMerged).asTypeOf(Vec(num, new PMPConfig())) 287 val addr = RegInit(init_value._2) // (Vec(num, UInt((PMPAddrBits-PMPOffBits).W))) 288 val mask = RegInit(init_value._3) // (Vec(num, UInt(PMPAddrBits.W))) 289 290 for (i <- entries.indices) { 291 entries(i).gen(cfgs(i), addr(i), mask(i)) 292 } 293 294 val cfg_mapping = (0 until num by pmpCfgPerCSR).map(i => {Map( 295 MaskedRegMap( 296 addr = cfgBase + pmpCfgIndex(i), 297 reg = cfgMerged(i/pmpCfgPerCSR), 298 wmask = WritableMask, 299 wfn = new PMPBase().write_cfg_vec(mask, addr, i) 300 )) 301 }).fold(Map())((a, b) => a ++ b) // ugly code, hit me if u have better codes 302 303 val addr_mapping = (0 until num).map(i => {Map( 304 MaskedRegMap( 305 addr = addrBase + i, 306 reg = addr(i), 307 wmask = WritableMask, 308 wfn = { if (i != num-1) entries(i).write_addr(entries(i+1).cfg, mask(i)) else entries(i).write_addr(mask(i)) }, 309 rmask = WritableMask, 310 rfn = new PMPBase().read_addr(entries(i).cfg) 311 )) 312 }).fold(Map())((a, b) => a ++ b) // ugly code, hit me if u have better codes. 313 314 cfg_mapping ++ addr_mapping 315 } 316} 317 318@chiselName 319class PMP(implicit p: Parameters) extends PMPXSModule with HasXSParameter with PMPMethod with PMAMethod with HasCSRConst { 320 val io = IO(new Bundle { 321 val distribute_csr = Flipped(new DistributedCSRIO()) 322 val pmp = Output(Vec(NumPMP, new PMPEntry())) 323 val pma = Output(Vec(NumPMA, new PMPEntry())) 324 }) 325 326 val w = io.distribute_csr.w 327 328 val pmp = Wire(Vec(NumPMP, new PMPEntry())) 329 val pma = Wire(Vec(NumPMA, new PMPEntry())) 330 331 val pmpMapping = pmp_gen_mapping(pmp_init, NumPMP, PmpcfgBase, PmpaddrBase, pmp) 332 val pmaMapping = pmp_gen_mapping(pma_init, NumPMA, PmacfgBase, PmaaddrBase, pma) 333 val mapping = pmpMapping ++ pmaMapping 334 335 val rdata = Wire(UInt(PMXLEN.W)) 336 MaskedRegMap.generate(mapping, w.bits.addr, rdata, w.valid, w.bits.data) 337 338 io.pmp := pmp 339 io.pma := pma 340} 341 342class PMPReqBundle(lgMaxSize: Int = 3)(implicit p: Parameters) extends PMPBundle { 343 val addr = Output(UInt(PMPAddrBits.W)) 344 val size = Output(UInt(log2Ceil(lgMaxSize+1).W)) 345 val cmd = Output(TlbCmd()) 346 347 def apply(addr: UInt, size: UInt, cmd: UInt) { 348 this.addr := addr 349 this.size := size 350 this.cmd := cmd 351 } 352 353 def apply(addr: UInt) { // req minimal permission and req align size 354 apply(addr, lgMaxSize.U, TlbCmd.read) 355 } 356 357 override def cloneType = (new PMPReqBundle(lgMaxSize)).asInstanceOf[this.type] 358} 359 360class PMPRespBundle(implicit p: Parameters) extends PMPBundle { 361 val ld = Output(Bool()) 362 val st = Output(Bool()) 363 val instr = Output(Bool()) 364 val mmio = Output(Bool()) 365 366 def |(resp: PMPRespBundle): PMPRespBundle = { 367 val res = Wire(new PMPRespBundle()) 368 res.ld := this.ld || resp.ld 369 res.st := this.st || resp.st 370 res.instr := this.instr || resp.instr 371 res.mmio := this.mmio || resp.mmio 372 res 373 } 374} 375 376trait PMPCheckMethod extends PMPConst { 377 def pmp_check(cmd: UInt, cfg: PMPConfig) = { 378 val resp = Wire(new PMPRespBundle) 379 resp.ld := TlbCmd.isRead(cmd) && !TlbCmd.isAtom(cmd) && !cfg.r 380 resp.st := (TlbCmd.isWrite(cmd) || TlbCmd.isAtom(cmd)) && !cfg.w 381 resp.instr := TlbCmd.isExec(cmd) && !cfg.x 382 resp.mmio := false.B 383 resp 384 } 385 386 def pmp_match_res(leaveHitMux: Boolean = false, valid: Bool = true.B)( 387 addr: UInt, 388 size: UInt, 389 pmpEntries: Vec[PMPEntry], 390 mode: UInt, 391 lgMaxSize: Int 392 ) = { 393 val num = pmpEntries.size 394 require(num == NumPMP) 395 396 val passThrough = if (pmpEntries.isEmpty) true.B else (mode > 1.U) 397 val pmpDefault = WireInit(0.U.asTypeOf(new PMPEntry())) 398 pmpDefault.cfg.r := passThrough 399 pmpDefault.cfg.w := passThrough 400 pmpDefault.cfg.x := passThrough 401 402 val match_vec = Wire(Vec(num+1, Bool())) 403 val cfg_vec = Wire(Vec(num+1, new PMPEntry())) 404 405 pmpEntries.zip(pmpDefault +: pmpEntries.take(num-1)).zipWithIndex.foreach{ case ((pmp, last_pmp), i) => 406 val is_match = pmp.is_match(addr, size, lgMaxSize, last_pmp) 407 val ignore = passThrough && !pmp.cfg.l 408 val aligned = pmp.aligned(addr, size, lgMaxSize, last_pmp) 409 410 val cur = WireInit(pmp) 411 cur.cfg.r := aligned && (pmp.cfg.r || ignore) 412 cur.cfg.w := aligned && (pmp.cfg.w || ignore) 413 cur.cfg.x := aligned && (pmp.cfg.x || ignore) 414 415// Mux(is_match, cur, prev) 416 match_vec(i) := is_match 417 cfg_vec(i) := cur 418 } 419 420 // default value 421 match_vec(num) := true.B 422 cfg_vec(num) := pmpDefault 423 424 if (leaveHitMux) { 425 ParallelPriorityMux(match_vec.map(RegEnable(_, init = false.B, valid)), RegEnable(cfg_vec, valid)) 426 } else { 427 ParallelPriorityMux(match_vec, cfg_vec) 428 } 429 } 430} 431 432class PMPCheckerEnv(implicit p: Parameters) extends PMPBundle { 433 val mode = UInt(2.W) 434 val pmp = Vec(NumPMP, new PMPEntry()) 435 val pma = Vec(NumPMA, new PMPEntry()) 436 437 def apply(mode: UInt, pmp: Vec[PMPEntry], pma: Vec[PMPEntry]): Unit = { 438 this.mode := mode 439 this.pmp := pmp 440 this.pma := pma 441 } 442} 443 444class PMPCheckIO(lgMaxSize: Int)(implicit p: Parameters) extends PMPBundle { 445 val check_env = Input(new PMPCheckerEnv()) 446 val req = Flipped(Valid(new PMPReqBundle(lgMaxSize))) // usage: assign the valid to fire signal 447 val resp = new PMPRespBundle() 448 449 def apply(mode: UInt, pmp: Vec[PMPEntry], pma: Vec[PMPEntry], req: Valid[PMPReqBundle]) = { 450 check_env.apply(mode, pmp, pma) 451 this.req := req 452 resp 453 } 454 455 def req_apply(valid: Bool, addr: UInt): Unit = { 456 this.req.valid := valid 457 this.req.bits.apply(addr) 458 } 459 460 def apply(mode: UInt, pmp: Vec[PMPEntry], pma: Vec[PMPEntry], valid: Bool, addr: UInt) = { 461 check_env.apply(mode, pmp, pma) 462 req_apply(valid, addr) 463 resp 464 } 465 override def cloneType: this.type = (new PMPCheckIO(lgMaxSize)).asInstanceOf[this.type] 466} 467 468@chiselName 469class PMPChecker 470( 471 lgMaxSize: Int = 3, 472 sameCycle: Boolean = false, 473 leaveHitMux: Boolean = false, 474 pmpUsed: Boolean = true 475)(implicit p: Parameters) extends PMPModule 476 with PMPCheckMethod 477 with PMACheckMethod 478{ 479 require(!(leaveHitMux && sameCycle)) 480 val io = IO(new PMPCheckIO(lgMaxSize)) 481 482 val req = io.req.bits 483 484 val res_pmp = pmp_match_res(leaveHitMux, io.req.valid)(req.addr, req.size, io.check_env.pmp, io.check_env.mode, lgMaxSize) 485 val res_pma = pma_match_res(leaveHitMux, io.req.valid)(req.addr, req.size, io.check_env.pma, io.check_env.mode, lgMaxSize) 486 487 val resp_pmp = pmp_check(req.cmd, res_pmp.cfg) 488 val resp_pma = pma_check(req.cmd, res_pma.cfg) 489 val resp = if (pmpUsed) (resp_pmp | resp_pma) else resp_pma 490 491 if (sameCycle || leaveHitMux) { 492 io.resp := resp 493 } else { 494 io.resp := RegEnable(resp, io.req.valid) 495 } 496}