1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.internal.naming.chiselName 22import chisel3.util._ 23import xiangshan.{HasXSParameter, XSModule} 24import xiangshan.backend.fu.util.HasCSRConst 25import xiangshan.cache.mmu.TlbCmd 26 27trait PMAMethod extends HasXSParameter with PMPConst { this: XSModule => 28 /** 29 def SimpleMemMapList = List( 30 // Base address Top address Width Description Mode (RWXIDSAC) 31 MemMap("h00_0000_0000", "h00_0FFF_FFFF", "h0", "Reserved", "RW"), 32 MemMap("h00_1000_0000", "h00_1FFF_FFFF", "h0", "QSPI_Flash", "RWX"), 33 MemMap("h00_2000_0000", "h00_2FFF_FFFF", "h0", "Reserved", "RW"), 34 MemMap("h00_3000_0000", "h00_3000_FFFF", "h0", "DMA", "RW"), 35 MemMap("h00_3001_0000", "h00_3004_FFFF", "h0", "GPU", "RWC"), 36 MemMap("h00_3005_0000", "h00_3006_FFFF", "h0", "USB/SDMMC", "RW"), 37 MemMap("h00_3007_0000", "h00_30FF_FFFF", "h0", "Reserved", "RW"), 38 MemMap("h00_3100_0000", "h00_3111_FFFF", "h0", "MMIO", "RW"), 39 MemMap("h00_3112_0000", "h00_37FF_FFFF", "h0", "Reserved", "RW"), 40 MemMap("h00_3800_0000", "h00_3800_FFFF", "h0", "CLINT", "RW"), 41 MemMap("h00_3801_0000", "h00_3801_FFFF", "h0", "BEU", "RW"), 42 MemMap("h00_3802_0000", "h00_3802_0FFF", "h0", "DebugModule", "RWX"), 43 MemMap("h00_3802_1000", "h00_3BFF_FFFF", "h0", "Reserved", ""), 44 MemMap("h00_3C00_0000", "h00_3FFF_FFFF", "h0", "PLIC", "RW"), 45 MemMap("h00_4000_0000", "h00_7FFF_FFFF", "h0", "PCIe", "RW"), 46 MemMap("h00_8000_0000", "h0F_FFFF_FFFF", "h0", "DDR", "RWXIDSA"), 47 ) 48 */ 49 50 def pma_init() : (Vec[UInt], Vec[UInt], Vec[UInt]) = { 51 // the init value is zero 52 // from 0 to num(default 16) - 1, lower priority 53 // according to simple map, 9 entries is needed, pick 6-14, leave 0-5 & 15 unusedcfgMerged.map(_ := 0.U) 54 55 val num = NumPMA 56 require(num >= 16) 57 val cfg = WireInit(0.U.asTypeOf(Vec(num, new PMPConfig()))) 58 59 val addr = Wire(Vec(num, UInt((PAddrBits-PMPOffBits).W))) 60 val mask = Wire(Vec(NumPMP, UInt(PAddrBits.W))) 61 addr := DontCare 62 mask := DontCare 63 64 addr(15) := 0x3FFFFFFFEL.U 65 cfg(15).a := 1.U; cfg(15).r := true.B; cfg(15).w := true.B; cfg(15).x := true.B; cfg(15).c := true.B; cfg(14).atomic := true.B 66 67 // use tor instead of napot, for napot may be confusing and hard to understand 68 addr(14) := shift_addr(0xFFFFFFFFFL) 69 cfg(14).a := 1.U; cfg(14).r := true.B; cfg(14).w := true.B; cfg(14).x := true.B; cfg(14).c := true.B; cfg(14).atomic := true.B 70 71 addr(13) := shift_addr(0x80000000L) 72 cfg(13).a := 1.U; cfg(13).r := true.B; cfg(13).w := true.B 73 74 addr(12) := shift_addr(0x3C000000) 75 cfg(12).a := 1.U 76 77 addr(11) := shift_addr(0x38021000) 78 cfg(11).a := 1.U; cfg(11).r := true.B; cfg(11).w := true.B; cfg(11).x := true.B 79 80 addr(10) := shift_addr(0x38020000) 81 cfg(10).a := 1.U; cfg(10).r := true.B; cfg(10).w := true.B 82 83 addr(9) := shift_addr( 0x30050000) 84 cfg(9).a := 1.U; cfg(9).r := true.B; cfg(9).w := true.B; cfg(8).c := true.B 85 86 addr(8) := shift_addr( 0x30010000) 87 cfg(8).a := 1.U; cfg(8).r := true.B; cfg(8).w := true.B 88 89 addr(7) := shift_addr( 0x20000000) 90 cfg(7).a := 1.U; cfg(7).r := true.B; cfg(7).w := true.B; cfg(7).x := true.B 91 92 addr(6) := shift_addr( 0x10000000) 93 cfg(6).a := 1.U; cfg(6).r := true.B; cfg(6).w := true.B 94 95 addr(5) := shift_addr(0) 96 97 val cfgInitMerge = cfg.asTypeOf(Vec(num/8, UInt(XLEN.W))) 98 (cfgInitMerge, addr, mask) 99 } 100 101 def shift_addr(addr: BigInt) = { 102 (addr >> 2).U 103 } 104} 105 106trait PMACheckMethod extends HasXSParameter with HasCSRConst { this: PMPChecker => 107 def pma_check(cmd: UInt, cfg: PMPConfig) = { 108 val resp = Wire(new PMPRespBundle) 109 resp.ld := TlbCmd.isRead(cmd) && !TlbCmd.isAtom(cmd) && !cfg.r 110 resp.st := (TlbCmd.isWrite(cmd) || TlbCmd.isAtom(cmd) && cfg.atomic) && !cfg.w 111 resp.instr := TlbCmd.isExec(cmd) && !cfg.x 112 resp.mmio := !cfg.c 113 resp 114 } 115 116 def pma_match_res(addr: UInt, size: UInt, pmaEntries: Vec[PMPEntry], mode: UInt, lgMaxSize: Int) = { 117 val num = pmaEntries.size 118 require(num == NumPMA) 119 // pma should always be checked, could not be ignored 120 // like amo and cached, it is the attribute not protection 121 // so it must have initialization. 122 require(!pmaEntries.isEmpty) 123 val default = if (pmaEntries.isEmpty) true.B else (mode > ModeS) 124 val pmpMinuxOne = WireInit(0.U.asTypeOf(new PMPEntry())) 125 126 val res = pmaEntries.zip(pmpMinuxOne +: pmaEntries.take(num-1)).zipWithIndex 127 .reverse.foldLeft(pmpMinuxOne) { case (prev, ((pma, last_pma), i)) => 128 val is_match = pma.is_match(addr, size, lgMaxSize, last_pma) 129 val aligned = pma.aligned(addr, size, lgMaxSize, last_pma) 130 131 val cur = WireInit(pma) 132 cur.cfg.r := aligned && pma.cfg.r 133 cur.cfg.w := aligned && pma.cfg.w 134 cur.cfg.x := aligned && pma.cfg.x 135 cur.cfg.atomic := aligned && pma.cfg.atomic 136 cur.cfg.c := aligned && pma.cfg.c 137 138 Mux(is_match, cur, prev) 139 } 140 res 141 } 142}