xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala (revision 6306fe335c2bca9aa17b8975c11e0e6116b494fd) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util.{Cat, ValidIO}
5import utility.SignExt
6import xiangshan.backend.fu.NewCSR.CSRBundles._
7import xiangshan.backend.fu.NewCSR.CSRDefines._
8import xiangshan.backend.fu.NewCSR.CSRFunc._
9import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, CSRWARLField => WARL, CSRWLRLField => WLRL, _}
10import xiangshan.backend.fu.NewCSR.CSRConfig._
11import xiangshan.backend.fu.NewCSR.CSREvents.TrapEntryHSEventSinkBundle
12
13import scala.collection.immutable.SeqMap
14
15trait SupervisorLevel { self: NewCSR with MachineLevel =>
16  val sie = Module(new CSRModule("Sie", new SieBundle) with HasMachineInterruptBundle with HasMachineDelegBundle{
17    val toMie = IO(new SieToMie)
18    // Sie is alias of mie.
19    // There are no regs in CSR sie.
20    regOut := mie.asUInt
21    // Ref: 7.1.3. Supervisor Interrupt Registers (sip and sie)
22    // The sip and sie registers are subsets of the mip and mie registers. Reading any
23    // implemented field, or writing any writable field, of sip/sie effects a read or write of the
24    // homonymous field of mip/mie.
25    // Ref: 3.1.9. Machine Interrupt Registers (mip and mie)
26    // Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If
27    // an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the
28    // sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie
29    // are **read-only zero**.
30    regOut.SSIE := Mux(mideleg.SSI.asBool, mie.SSIE.asUInt, 0.U)
31    regOut.STIE := Mux(mideleg.STI.asBool, mie.STIE.asUInt, 0.U)
32    regOut.SEIE := Mux(mideleg.SEI.asBool, mie.SEIE.asUInt, 0.U)
33
34    toMie.SSIE.valid := wen && mideleg.SSI.asBool
35    toMie.STIE.valid := wen && mideleg.STI.asBool
36    toMie.SEIE.valid := wen && mideleg.SEI.asBool
37    toMie.SSIE.bits := wdata.SSIE
38    toMie.STIE.bits := wdata.STIE
39    toMie.SEIE.bits := wdata.SEIE
40  })
41    .setAddr(0x104)
42
43  val stvec = Module(new CSRModule("Stvec", new XtvecBundle))
44    .setAddr(0x105)
45
46  val scounteren = Module(new CSRModule("Scounteren", new Counteren))
47    .setAddr(0x106)
48
49  val senvcfg = Module(new CSRModule("Senvcfg", new Envcfg))
50    .setAddr(0x10A)
51
52  val sscratch = Module(new CSRModule("Sscratch"))
53    .setAddr(0x140)
54
55  val sepc = Module(new CSRModule("Sepc", new Epc) with TrapEntryHSEventSinkBundle {
56    rdata := SignExt(Cat(reg.epc.asUInt, 0.U(1.W)), XLEN)
57  })
58    .setAddr(0x141)
59
60  val scause = Module(new CSRModule("Scause", new CauseBundle) with TrapEntryHSEventSinkBundle)
61    .setAddr(0x142)
62
63  val stval = Module(new CSRModule("Stval") with TrapEntryHSEventSinkBundle)
64    .setAddr(0x143)
65
66  val sip = Module(new CSRModule("Sip", new SipBundle) with HasMachineInterruptBundle with HasMachineDelegBundle {
67    val toMip = IO(new SipToMip)
68
69    // Ref: 7.1.3. Supervisor Interrupt Registers (sip and sie)
70    // The sip and sie registers are subsets of the mip and mie registers. Reading any
71    // implemented field, or writing any writable field, of sip/sie effects a read or write of the
72    // homonymous field of mip/mie.
73    // Ref: 3.1.9. Machine Interrupt Registers (mip and mie)
74    // Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If
75    // an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the
76    // sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie
77    // are **read-only zero**.
78
79    regOut.SSIP := Mux(mideleg.SSI.asUInt.asBool, mip.SSIP.asUInt, 0.U)
80    regOut.STIP := Mux(mideleg.STI.asUInt.asBool, mip.STIP.asUInt, 0.U)
81    regOut.SEIP := Mux(mideleg.SEI.asUInt.asBool, mip.SEIP.asUInt, 0.U)
82
83    toMip.SSIP.valid := wen && mideleg.SSI.asBool
84    toMip.SSIP.bits := wdata.SSIP
85  })
86    .setAddr(0x144)
87
88  val stimecmp = Module(new CSRModule("Stimecmp"))
89    .setAddr(0x14D)
90
91  val satp = Module(new CSRModule("Satp", new SatpBundle) {
92    // If satp is written with an unsupported MODE,
93    // the entire write has no effect; no fields in satp are modified.
94    when (wen && wdata.MODE.isLegal) {
95      reg := wdata
96    }.otherwise {
97      reg := reg
98    }
99  })
100    .setAddr(0x180)
101
102  val supervisorLevelCSRMods: Seq[CSRModule[_]] = Seq(
103    sie,
104    stvec,
105    scounteren,
106    senvcfg,
107    sscratch,
108    sepc,
109    scause,
110    stval,
111    sip,
112    stimecmp,
113    satp,
114  )
115
116  val supervisorLevelCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], Data)] = SeqMap(
117    0x100 -> (mstatus.wAliasSstatus, mstatus.sstatus),
118  ) ++ SeqMap.from(
119    supervisorLevelCSRMods.map(csr => (csr.addr -> (csr.w, csr.rdata))).iterator
120  )
121
122  val supervisorLevelCSROutMap: SeqMap[Int, UInt] = SeqMap(
123    0x100 -> mstatus.sstatus.asUInt,
124  ) ++ SeqMap.from(
125    supervisorLevelCSRMods.map(csr => (csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt)).iterator
126  )
127}
128
129class SstatusBundle extends CSRBundle {
130  val SIE  = CSRWARLField   (1, wNoFilter)
131  val SPIE = CSRWARLField   (5, wNoFilter)
132  val UBE  = CSRROField     (6)
133  val SPP  = CSRWARLField   (8, wNoFilter)
134  val VS   = ContextStatus  (10, 9)
135  val FS   = ContextStatus  (14, 13)
136  val XS   = ContextStatusRO(16, 15).withReset(0.U)
137  val SUM  = CSRWARLField   (18, wNoFilter)
138  val MXR  = CSRWARLField   (19, wNoFilter)
139  val UXL  = XLENField      (33, 32).withReset(XLENField.XLEN64)
140  val SD   = CSRROField     (63, (_, _) => FS === ContextStatus.Dirty || VS === ContextStatus.Dirty)
141}
142
143class SieBundle extends InterruptEnableBundle {
144  this.getALL.foreach(_.setRO().withReset(0.U))
145  this.SSIE.setRW().withReset(0.U)
146  this.STIE.setRW().withReset(0.U)
147  this.SEIE.setRW().withReset(0.U)
148  // Todo: LCOFIE
149}
150
151class SipBundle extends InterruptPendingBundle {
152  this.getALL.foreach(_.setRO().withReset(0.U))
153  // If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller
154  // If implemented, STIP is read-only in sip, and is set and cleared by the execution environment.
155  // If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller.
156  this.SSIP.setRW().withReset(0.U)
157  // Todo: LCOFIE
158}
159
160class SatpBundle extends CSRBundle {
161  final val PPN_msb = PAddrWidth - AddrWidthInPage - 1
162  val MODE = SatpMode(63, 60, null).withReset(SatpMode.Bare)
163  // WARL in privileged spec.
164  // RW, since we support max width of ASID
165  val ASID = RW(44 - 1 + ASIDLEN, 44)
166  val PPN  = RW(PPN_msb, 0)
167}
168
169class SieToMie extends Bundle {
170  val SSIE = ValidIO(RW(0))
171  val STIE = ValidIO(RW(0))
172  val SEIE = ValidIO(RW(0))
173}
174
175class SipToMip extends Bundle {
176  val SSIP = ValidIO(RW(0))
177}
178