xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala (revision 25dc4a827ee27e3ccbaf02e8e5134872cba28fcd) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util.ValidIO
5import xiangshan.backend.fu.NewCSR.CSRBundles._
6import xiangshan.backend.fu.NewCSR.CSRDefines._
7import xiangshan.backend.fu.NewCSR.CSRFunc._
8import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, CSRWARLField => WARL, CSRWLRLField => WLRL, _}
9import xiangshan.backend.fu.NewCSR.CSRConfig._
10import xiangshan.backend.fu.NewCSR.CSREvents.TrapEntryHSEventSinkBundle
11
12import scala.collection.immutable.SeqMap
13
14trait SupervisorLevel { self: NewCSR with MachineLevel =>
15  val sie = Module(new CSRModule("Sie", new SieBundle) with HasMachineInterruptBundle with HasMachineDelegBundle{
16    val toMie = IO(new SieToMie)
17    // Ref: 7.1.3. Supervisor Interrupt Registers (sip and sie)
18    // The sip and sie registers are subsets of the mip and mie registers. Reading any
19    // implemented field, or writing any writable field, of sip/sie effects a read or write of the
20    // homonymous field of mip/mie.
21    // Ref: 3.1.9. Machine Interrupt Registers (mip and mie)
22    // Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If
23    // an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the
24    // sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie
25    // are **read-only zero**.
26    rdata.SSIE := Mux(mideleg.SSI.asBool, mie.SSIE.asUInt, 0.U)
27    rdata.STIE := Mux(mideleg.STI.asBool, mie.STIE.asUInt, 0.U)
28    rdata.SEIE := Mux(mideleg.SEI.asBool, mie.SEIE.asUInt, 0.U)
29
30    toMie.SSIE.valid := wen && mideleg.SSI.asBool
31    toMie.STIE.valid := wen && mideleg.STI.asBool
32    toMie.SEIE.valid := wen && mideleg.SEI.asBool
33    toMie.SSIE.bits := wdata.SSIE
34    toMie.STIE.bits := wdata.STIE
35    toMie.SEIE.bits := wdata.SEIE
36  })
37    .setAddr(0x104)
38
39  val stvec = Module(new CSRModule("Stvec", new XtvecBundle))
40    .setAddr(0x105)
41
42  val scounteren = Module(new CSRModule("Scounteren", new Counteren))
43    .setAddr(0x106)
44
45  val senvcfg = Module(new CSRModule("Senvcfg", new Envcfg))
46    .setAddr(0x10A)
47
48  val sscratch = Module(new CSRModule("Sscratch"))
49    .setAddr(0x140)
50
51  val sepc = Module(new CSRModule("Sepc", new Epc) with TrapEntryHSEventSinkBundle)
52    .setAddr(0x141)
53
54  val scause = Module(new CSRModule("Scause", new CauseBundle) with TrapEntryHSEventSinkBundle)
55    .setAddr(0x142)
56
57  val stval = Module(new CSRModule("Stval") with TrapEntryHSEventSinkBundle)
58    .setAddr(0x143)
59
60  val sip = Module(new CSRModule("Sip", new SipBundle) with HasMachineInterruptBundle with HasMachineDelegBundle {
61    val toMip = IO(new SipToMip)
62
63    // Ref: 7.1.3. Supervisor Interrupt Registers (sip and sie)
64    // The sip and sie registers are subsets of the mip and mie registers. Reading any
65    // implemented field, or writing any writable field, of sip/sie effects a read or write of the
66    // homonymous field of mip/mie.
67    // Ref: 3.1.9. Machine Interrupt Registers (mip and mie)
68    // Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If
69    // an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the
70    // sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie
71    // are **read-only zero**.
72
73    rdata.SSIP := Mux(mideleg.SSI.asUInt.asBool, mip.SSIP.asUInt, 0.U)
74    rdata.STIP := Mux(mideleg.STI.asUInt.asBool, mip.STIP.asUInt, 0.U)
75    rdata.SEIP := Mux(mideleg.SEI.asUInt.asBool, mip.SEIP.asUInt, 0.U)
76
77    toMip.SSIP.valid := wen && mideleg.SSI.asBool
78    toMip.SSIP.bits := wdata.SSIP
79  })
80    .setAddr(0x144)
81
82  val satp = Module(new CSRModule("Satp", new SatpBundle))
83    .setAddr(0x180)
84
85  val supervisorLevelCSRMods: Seq[CSRModule[_]] = Seq(
86    sie,
87    stvec,
88    scounteren,
89    senvcfg,
90    sscratch,
91    sepc,
92    scause,
93    stval,
94    sip,
95    satp,
96  )
97
98  val supervisorLevelCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], Data)] = SeqMap(
99    0x100 -> (mstatus.wAliasSstatus, mstatus.sstatus),
100  ) ++ SeqMap.from(
101    supervisorLevelCSRMods.map(csr => (csr.addr -> (csr.w, csr.rdata.asInstanceOf[CSRBundle].asUInt))).iterator
102  )
103
104  val supervisorLevelCSROutMap: SeqMap[Int, UInt] = SeqMap(
105    0x100 -> mstatus.sstatus.asUInt,
106  ) ++ SeqMap.from(
107    supervisorLevelCSRMods.map(csr => (csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt)).iterator
108  )
109}
110
111class SstatusBundle extends CSRBundle {
112  val SIE  = CSRWARLField   (1, wNoFilter)
113  val SPIE = CSRWARLField   (5, wNoFilter)
114  val UBE  = CSRROField     (6)
115  val SPP  = CSRWARLField   (8, wNoFilter)
116  val VS   = ContextStatus  (10, 9)
117  val FS   = ContextStatus  (14, 13)
118  val XS   = ContextStatusRO(16, 15).withReset(0.U)
119  val SUM  = CSRWARLField   (18, wNoFilter)
120  val MXR  = CSRWARLField   (19, wNoFilter)
121  val UXL  = XLENField      (33, 32).withReset(XLENField.XLEN64)
122  val SD   = CSRROField     (63, (_, _) => FS === ContextStatus.Dirty || VS === ContextStatus.Dirty)
123}
124
125class SieBundle extends InterruptEnableBundle {
126  this.getALL.foreach(_.setRO())
127  this.SSIE.setRW()
128  this.STIE.setRW()
129  this.SEIE.setRW()
130  // Todo: LCOFIE
131}
132
133class SipBundle extends InterruptPendingBundle {
134  this.getALL.foreach(_.setRO())
135  // If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller
136  // If implemented, STIP is read-only in sip, and is set and cleared by the execution environment.
137  // If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller.
138  this.SSIP.setRW()
139  // Todo: LCOFIE
140}
141
142class SatpBundle extends CSRBundle {
143  val MODE = SatpMode(63, 60, null).withReset(SatpMode.Bare)
144  // WARL in privileged spec.
145  // RW, since we support max width of ASID
146  val ASID = RW(44 - 1 + ASIDLEN, 44)
147  val PPN  = RW(43, 0)
148}
149
150class SieToMie extends Bundle {
151  val SSIE = ValidIO(RW(0))
152  val STIE = ValidIO(RW(0))
153  val SEIE = ValidIO(RW(0))
154}
155
156class SipToMip extends Bundle {
157  val SSIP = ValidIO(RW(0))
158}
159