xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala (revision 039cdc35f5f3b68b6295ec5ace90f22a77322e02) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util.ValidIO
5import xiangshan.backend.fu.NewCSR.CSRBundles._
6import xiangshan.backend.fu.NewCSR.CSRDefines._
7import xiangshan.backend.fu.NewCSR.CSRFunc._
8import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, CSRWARLField => WARL, CSRWLRLField => WLRL, _}
9import xiangshan.backend.fu.NewCSR.CSRConfig._
10
11import scala.collection.immutable.SeqMap
12
13trait SupervisorLevel { self: NewCSR with MachineLevel =>
14  val sie = Module(new CSRModule("Sie", new SieBundle) with HasMachineInterruptBundle with HasMachineDelegBundle{
15    val toMie = IO(new SieToMie)
16    // Ref: 7.1.3. Supervisor Interrupt Registers (sip and sie)
17    // The sip and sie registers are subsets of the mip and mie registers. Reading any
18    // implemented field, or writing any writable field, of sip/sie effects a read or write of the
19    // homonymous field of mip/mie.
20    // Ref: 3.1.9. Machine Interrupt Registers (mip and mie)
21    // Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If
22    // an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the
23    // sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie
24    // are **read-only zero**.
25    rdata.SSIE := Mux(mideleg.SSI.asBool, mie.SSIE.asUInt, 0.U)
26    rdata.STIE := Mux(mideleg.STI.asBool, mie.STIE.asUInt, 0.U)
27    rdata.SEIE := Mux(mideleg.SEI.asBool, mie.SEIE.asUInt, 0.U)
28
29    toMie.SSIE.valid := wen && mideleg.SSI.asBool
30    toMie.STIE.valid := wen && mideleg.STI.asBool
31    toMie.SEIE.valid := wen && mideleg.SEI.asBool
32    toMie.SSIE.bits := wdata.SSIE
33    toMie.STIE.bits := wdata.STIE
34    toMie.SEIE.bits := wdata.SEIE
35  })
36    .setAddr(0x104)
37
38  val stvec = Module(new CSRModule("Stvec", new XtvecBundle))
39    .setAddr(0x105)
40
41  val scounteren = Module(new CSRModule("Scounteren", new Counteren))
42    .setAddr(0x106)
43
44  val senvcfg = Module(new CSRModule("Senvcfg", new Envcfg))
45    .setAddr(0x10A)
46
47  val sscratch = Module(new CSRModule("Sscratch"))
48    .setAddr(0x140)
49
50  val sepc = Module(new CSRModule("Sepc", new Epc))
51    .setAddr(0x141)
52
53  val scause = Module(new CSRModule("Scause", new CauseBundle))
54    .setAddr(0x142)
55
56  val stval = Module(new CSRModule("Stval"))
57    .setAddr(0x143)
58
59  val sip = Module(new CSRModule("Sip", new SipBundle) with HasMachineInterruptBundle with HasMachineDelegBundle {
60    val toMip = IO(new SipToMip)
61
62    // Ref: 7.1.3. Supervisor Interrupt Registers (sip and sie)
63    // The sip and sie registers are subsets of the mip and mie registers. Reading any
64    // implemented field, or writing any writable field, of sip/sie effects a read or write of the
65    // homonymous field of mip/mie.
66    // Ref: 3.1.9. Machine Interrupt Registers (mip and mie)
67    // Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If
68    // an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the
69    // sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie
70    // are **read-only zero**.
71
72    rdata.SSIP := Mux(mideleg.SSI.asUInt.asBool, mip.SSIP.asUInt, 0.U)
73    rdata.STIP := Mux(mideleg.STI.asUInt.asBool, mip.STIP.asUInt, 0.U)
74    rdata.SEIP := Mux(mideleg.SEI.asUInt.asBool, mip.SEIP.asUInt, 0.U)
75
76    toMip.SSIP.valid := wen && mideleg.SSI.asBool
77    toMip.SSIP.bits := wdata.SSIP
78  })
79    .setAddr(0x144)
80
81  val satp = Module(new CSRModule("Satp", new SatpBundle))
82    .setAddr(0x180)
83
84  val supervisorLevelCSRMods: Seq[CSRModule[_]] = Seq(
85    sie,
86    stvec,
87    scounteren,
88    senvcfg,
89    sscratch,
90    sepc,
91    scause,
92    stval,
93    sip,
94    satp,
95  )
96
97  val supervisorLevelCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], Data)] = SeqMap(
98    0x100 -> (mstatus.wAliasSstatus, mstatus.sstatus),
99  ) ++ SeqMap.from(
100    supervisorLevelCSRMods.map(csr => (csr.addr -> (csr.w, csr.rdata.asInstanceOf[CSRBundle].asUInt))).iterator
101  )
102}
103
104class SstatusBundle extends CSRBundle {
105  val SIE  = CSRWARLField   (1, wNoFilter)
106  val SPIE = CSRWARLField   (5, wNoFilter)
107  val UBE  = CSRROField     (6)
108  val SPP  = CSRWARLField   (8, wNoFilter)
109  val VS   = ContextStatus  (10, 9)
110  val FS   = ContextStatus  (14, 13)
111  val XS   = ContextStatusRO(16, 15).withReset(0.U)
112  val SUM  = CSRWARLField   (18, wNoFilter)
113  val MXR  = CSRWARLField   (19, wNoFilter)
114  val UXL  = XLENField      (33, 32).withReset(XLENField.XLEN64)
115  val SD   = CSRROField     (63, (_, _) => FS === ContextStatus.Dirty || VS === ContextStatus.Dirty)
116}
117
118class SieBundle extends InterruptEnableBundle {
119  this.getALL.foreach(_.setRO())
120  this.SSIE.setRW()
121  this.STIE.setRW()
122  this.SEIE.setRW()
123  // Todo: LCOFIE
124}
125
126class SipBundle extends InterruptPendingBundle {
127  this.getALL.foreach(_.setRO())
128  // If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller
129  // If implemented, STIP is read-only in sip, and is set and cleared by the execution environment.
130  // If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller.
131  this.SSIP.setRW()
132  // Todo: LCOFIE
133}
134
135class SatpBundle extends CSRBundle {
136  val MODE = SatpMode(63, 60, null).withReset(SatpMode.Bare)
137  // WARL in privileged spec.
138  // RW, since we support max width of ASID
139  val ASID = RW(44 - 1 + ASIDLEN, 44)
140  val PPN  = RW(43, 0)
141}
142
143class SieToMie extends Bundle {
144  val SSIE = ValidIO(RW(0))
145  val STIE = ValidIO(RW(0))
146  val SEIE = ValidIO(RW(0))
147}
148
149class SipToMip extends Bundle {
150  val SSIP = ValidIO(RW(0))
151}
152