1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW} 5import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 6 7 8class SstateenBundle0 extends CSRBundle { 9 override val len: Int = 32 10 val JVT = RO(2).withReset(0.U) // jvt CSR in Zcmt extension 11 val FCSR = RO(1).withReset(0.U) // fp inst op 'x' register not f in Zfinx, Zdinx; misa.F =1 -> RO 0; misa.F=0 & this=0 -> V/EX_II 12 val C = RW(0).withReset(1.U) // custom state enable, [m|h|s]stateen is standard, not custom. 13} 14 15class HstateenBundle0 extends SstateenBundle0 { 16 override val len: Int = 64 17 val SE0 = RW(63).withReset(1.U) // m: [h|s]stateen h: sstateen 18 val ENVCFG = RW(62).withReset(1.U) // m: [h|s]envcfg h: senvcfg 19 // Bits in any stateen CSR that are defined to control state that a hart doesn’t implement are read-only 20 // zeros for that hart. Smcsrind/Sscsrind is not implemented. 21 val CSRIND = RO(60).withReset(1.U) // m: [vs|s]iselect, [vs|s]ireg* h: siselect, sireg* 22 val AIA = RW(59).withReset(1.U) // all other state added by the AIA and not controlled by bits 60 and 58 23 val IMSIC = RW(58).withReset(1.U) // m: [vs|s]topei h: stopei 24 val CONTEXT = RO(57).withReset(0.U) // m: [h|s]context in Sdtrig h: scontext 25} 26 27class MstateenBundle0 extends HstateenBundle0 { 28 val P1P13 = RO(56).withReset(0.U) // hedelegh in Priv Spec V1.13 29} 30 31trait HasStateen0Bundle { self: CSRModule[_] => 32 val fromMstateen0 = IO(Input(new MstateenBundle0)) 33 val fromHstateen0 = IO(Input(new HstateenBundle0)) 34 val privState = IO(Input(new PrivState)) 35} 36