1*a67fd0f5SGuanghui Chengpackage xiangshan.backend.fu.NewCSR 2*a67fd0f5SGuanghui Cheng 3*a67fd0f5SGuanghui Chengimport chisel3._ 4*a67fd0f5SGuanghui Chengimport freechips.rocketchip.rocket.CSRs 5*a67fd0f5SGuanghui Chengimport org.chipsalliance.cde.config.Parameters 6*a67fd0f5SGuanghui Chengimport xiangshan.{DistributedCSRIO, XSModule} 7*a67fd0f5SGuanghui Chengimport xiangshan.backend.fu.NewCSR.CSRConfig._ 8*a67fd0f5SGuanghui Cheng 9*a67fd0f5SGuanghui Chengclass PFEvent(implicit p: Parameters) extends XSModule { 10*a67fd0f5SGuanghui Cheng val io = IO(new Bundle { 11*a67fd0f5SGuanghui Cheng val distribute_csr = Flipped(new DistributedCSRIO()) 12*a67fd0f5SGuanghui Cheng val hpmevent = Output(Vec(perfCntNum, UInt(XLEN.W))) 13*a67fd0f5SGuanghui Cheng }) 14*a67fd0f5SGuanghui Cheng 15*a67fd0f5SGuanghui Cheng val w = io.distribute_csr.w 16*a67fd0f5SGuanghui Cheng 17*a67fd0f5SGuanghui Cheng val perfEvents: Seq[CSRModule[_]] = (0 until perfCntNum).map(num => 18*a67fd0f5SGuanghui Cheng Module(new CSRModule(s"perfEvents", new MhpmeventBundle)) 19*a67fd0f5SGuanghui Cheng .setAddr(CSRs.mhpmevent3 + num) 20*a67fd0f5SGuanghui Cheng ) 21*a67fd0f5SGuanghui Cheng 22*a67fd0f5SGuanghui Cheng perfEvents.zip(io.hpmevent).map{case(perf, out) => { 23*a67fd0f5SGuanghui Cheng perf.w.wen := w.valid && (w.bits.addr === perf.addr.U) 24*a67fd0f5SGuanghui Cheng perf.w.wdata := w.bits.data 25*a67fd0f5SGuanghui Cheng out := perf.rdata 26*a67fd0f5SGuanghui Cheng }} 27*a67fd0f5SGuanghui Cheng}