xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala (revision 8b7dc6f554c87e939d588726affdf7b89b1aad5b) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import freechips.rocketchip.rocket.CSRs
6import difftest._
7import org.chipsalliance.cde.config.Parameters
8import top.{ArgParser, Generator}
9import utility.{DataHoldBypass, SignExt, ZeroExt}
10import utils.OptionWrapper
11import xiangshan.backend.fu.NewCSR.CSRBundles.{CSRCustomState, PrivState, RobCommitCSR}
12import xiangshan.backend.fu.NewCSR.CSRDefines.{ContextStatus, PrivMode, SatpMode, VirtMode}
13import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._
14import xiangshan.backend.fu.NewCSR.CSREvents.{CSREvents, DretEventSinkBundle, EventUpdatePrivStateOutput, MretEventSinkBundle, SretEventSinkBundle, TrapEntryDEventSinkBundle, TrapEntryEventInput, TrapEntryHSEventSinkBundle, TrapEntryMEventSinkBundle, TrapEntryVSEventSinkBundle}
15import xiangshan.backend.fu.fpu.Bundles.Frm
16import xiangshan.backend.fu.vector.Bundles.{Vl, Vstart, Vxrm, Vxsat}
17import xiangshan.backend.fu.wrapper.CSRToDecode
18import xiangshan.{FrontendTdataDistributeIO, HasXSParameter, MemTdataDistributeIO, XSCoreParamsKey, XSTileKey}
19import xiangshan._
20import xiangshan.backend.fu.util.CSRConst
21
22import scala.collection.immutable.SeqMap
23
24object CSRConfig {
25  final val GEILEN = 63
26
27  final val ASIDLEN = 16 // the length of ASID of XS implementation
28
29  final val ASIDMAX = 16 // the max value of ASIDLEN defined by spec
30
31  final val HIIDWidth = 12 // support Hvictl[27:16](IID)
32
33  final val VMIDLEN = 14 // the length of VMID of XS implementation
34
35  final val VMIDMAX = 14 // the max value of VMIDLEN defined by spec
36
37  // the width of VGEIN
38  final val VGEINWidth = 6
39
40  final val VaddrMaxWidth = 41 // only Sv39 and Sv39x4
41
42  final val XLEN = 64 // Todo: use XSParams
43
44  final val VLEN = 128
45
46  // Since we need macro to compute the width of CSR field, the input of macro should be the value that can be computed
47  // at compile time. The log2Up function cannot be used as meta-programming function, so we use litral value here
48  // log2Up(128 + 1), hold 0~128
49  final val VlWidth = 8
50
51  final val PAddrWidth = 36
52
53  final val AddrWidthInPage = 12
54
55  final val PMPAddrWidth = 36
56
57  final val PMPOffBits = 2
58
59  final val PMPAddrBits = PMPAddrWidth - PMPOffBits
60
61  // trigger
62  final val triggerNum    = 4     // Todo: use XSParams
63  final val tselectWidth  = 2     // log2Up(triggerNum)
64}
65
66class NewCSR(implicit val p: Parameters) extends Module
67  with HasXSParameter
68  with MachineLevel
69  with SupervisorLevel
70  with HypervisorLevel
71  with VirtualSupervisorLevel
72  with Unprivileged
73  with CSRAIA
74  with HasExternalInterruptBundle
75  with SupervisorMachineAliasConnect
76  with CSREvents
77  with DebugLevel
78  with CSRCustom
79  with CSRPMP
80{
81
82  import CSRConfig._
83
84  val io = IO(new Bundle {
85    val fromTop = Input(new Bundle {
86      val hartId = UInt(hartIdLen.W)
87    })
88    val in = Input(new Bundle {
89      val wen = Bool()
90      val ren = Bool()
91      val addr = UInt(12.W)
92      val wdata = UInt(64.W)
93    })
94    val fromMem = Input(new Bundle {
95      val excpVA  = UInt(VaddrMaxWidth.W)
96      val excpGPA = UInt(VaddrMaxWidth.W) // Todo: use guest physical address width
97    })
98    val fromRob = Input(new Bundle {
99      val trap = ValidIO(new Bundle {
100        val pc = UInt(VaddrMaxWidth.W)
101        val instr = UInt(32.W)
102        val trapVec = UInt(64.W)
103        val singleStep = Bool()
104        val triggerCf = new TriggerCf
105        val crossPageIPFFix = Bool()
106        val isInterrupt = Bool()
107      })
108      val commit = Input(new RobCommitCSR)
109    })
110    val mret = Input(Bool())
111    val sret = Input(Bool())
112    val dret = Input(Bool())
113    val wfi  = Input(Bool())
114    val ebreak = Input(Bool())
115
116    val out = Output(new Bundle {
117      val EX_II = Bool()
118      val EX_VI = Bool()
119      val flushPipe = Bool()
120      val rData = UInt(64.W)
121      val targetPc = UInt(VaddrMaxWidth.W)
122      val regOut = UInt(64.W)
123      val privState = new PrivState
124      val interrupt = Bool()
125      val wfiEvent = Bool()
126      val tvm = Bool()
127      val vtvm = Bool()
128      // fp
129      val fpState = new Bundle {
130        val off = Bool()
131        val frm = Frm()
132      }
133      // vec
134      val vecState = new Bundle {
135        val vstart = Vstart()
136        val vxsat = Vxsat()
137        val vxrm = Vxrm()
138        val vcsr = UInt(XLEN.W)
139        val vl = Vl()
140        val vtype = UInt(XLEN.W)
141        val vlenb = UInt(XLEN.W)
142        val off = Bool()
143      }
144      // perf
145      val isPerfCnt = Bool()
146      // debug
147      val debugMode = Bool()
148      val singleStepFlag = Bool()
149      // trigger
150      val frontendTrigger = new FrontendTdataDistributeIO()
151      val memTrigger = new MemTdataDistributeIO()
152      // custom
153      val custom = new CSRCustomState
154    })
155    // tlb
156    val tlb = Output(new Bundle {
157      val satpASIDChanged = Bool()
158      val vsatpASIDChanged = Bool()
159      val hgatpVMIDChanged = Bool()
160      val satp = new SatpBundle
161      val vsatp = new SatpBundle
162      val hgatp = new HgatpBundle
163      val mxr = Bool()
164      val sum = Bool()
165      val vmxr = Bool()
166      val vsum = Bool()
167      val spvp = Bool()
168      val imode = UInt(2.W)
169      val dmode = UInt(2.W)
170    })
171
172    val toDecode = new CSRToDecode
173  })
174
175  val toAIA   = IO(Output(new CSRToAIABundle))
176  val fromAIA = IO(Flipped(Output(new AIAToCSRBundle)))
177
178  dontTouch(toAIA)
179  dontTouch(fromAIA)
180
181  val wen   = io.in.wen
182  val addr  = io.in.addr
183  val wdata = io.in.wdata
184
185  val ren   = io.in.ren
186  val raddr = io.in.addr
187
188  val hasTrap = io.fromRob.trap.valid
189  val trapVec = io.fromRob.trap.bits.trapVec
190  val trapPC = io.fromRob.trap.bits.pc
191  val trapIsInterrupt = io.fromRob.trap.bits.isInterrupt
192  val trapIsCrossPageIPF = io.fromRob.trap.bits.crossPageIPFFix
193  val triggerCf = io.fromRob.trap.bits.triggerCf
194
195  // debug_intrrupt
196  val debugIntrEnable = RegInit(true.B) // debug interrupt will be handle only when debugIntrEnable
197  val debugIntr = platformIRP.debugIP && debugIntrEnable
198
199  // CSR Privilege State
200  val PRVM = RegInit(PrivMode(0), PrivMode.M)
201  val V = RegInit(VirtMode(0), VirtMode.Off)
202  val debugMode = RegInit(false.B)
203
204  private val privState = Wire(new PrivState)
205  privState.PRVM := PRVM
206  privState.V := V
207
208  private val isModeM              = privState.isModeM
209  private val (isModeHS, isModeHU) = (privState.isModeHS, privState.isModeHU)
210  private val (isModeVS, isModeVU) = (privState.isModeVS, privState.isModeVU)
211
212  val permitMod = Module(new CSRPermitModule)
213
214  private val wenLegal = permitMod.io.out.hasLegalWen
215
216  val legalSret = permitMod.io.out.hasLegalSret
217  val legalMret = permitMod.io.out.hasLegalMret
218  val isDret = io.dret // Todo: check permission
219  val isWfi  = permitMod.io.out.hasLegalWfi
220
221  var csrRwMap: SeqMap[Int, (CSRAddrWriteBundle[_], Data)] =
222    machineLevelCSRMap ++
223    supervisorLevelCSRMap ++
224    hypervisorCSRMap ++
225    virtualSupervisorCSRMap ++
226    unprivilegedCSRMap ++
227    debugCSRMap ++
228    aiaCSRMap ++
229    customCSRMap ++
230    pmpCSRMap
231
232  val csrMods: Seq[CSRModule[_]] =
233    machineLevelCSRMods ++
234    supervisorLevelCSRMods ++
235    hypervisorCSRMods ++
236    virtualSupervisorCSRMods ++
237    unprivilegedCSRMods ++
238    debugCSRMods ++
239    aiaCSRMods ++
240    customCSRMods ++
241    pmpCSRMods
242
243  var csrOutMap: SeqMap[Int, UInt] =
244    machineLevelCSROutMap ++
245    supervisorLevelCSROutMap ++
246    hypervisorCSROutMap ++
247    virtualSupervisorCSROutMap ++
248    unprivilegedCSROutMap ++
249    debugCSROutMap ++
250    aiaCSROutMap ++
251    customCSROutMap ++
252    pmpCSROutMap
253
254  // interrupt
255  val intrMod = Module(new InterruptFilter)
256  intrMod.io.in.privState := privState
257  intrMod.io.in.mstatusMIE := mstatus.regOut.MIE.asBool
258  intrMod.io.in.sstatusSIE := mstatus.regOut.SIE.asBool
259  intrMod.io.in.vsstatusSIE := vsstatus.regOut.SIE.asBool
260  intrMod.io.in.mip := mip.rdata.asUInt
261  intrMod.io.in.mie := mie.rdata.asUInt
262  intrMod.io.in.mideleg := mideleg.rdata.asUInt
263  intrMod.io.in.sip := sip.rdata.asUInt
264  intrMod.io.in.sie := sie.rdata.asUInt
265  intrMod.io.in.hip := hip.rdata.asUInt
266  intrMod.io.in.hie := hie.rdata.asUInt
267  intrMod.io.in.hideleg := hideleg.rdata.asUInt
268  intrMod.io.in.vsip := vsip.rdata.asUInt
269  intrMod.io.in.vsie := vsie.rdata.asUInt
270  intrMod.io.in.hvictl := hvictl.rdata.asUInt
271  intrMod.io.in.hstatus := hstatus.rdata.asUInt
272  intrMod.io.in.mtopei := mtopei.rdata.asUInt
273  intrMod.io.in.stopei := stopei.rdata.asUInt
274  intrMod.io.in.vstopei := vstopei.rdata.asUInt
275  intrMod.io.in.hviprio1 := hviprio1.rdata.asUInt
276  intrMod.io.in.hviprio2 := hviprio2.rdata.asUInt
277  intrMod.io.in.miprios := Cat(miregiprios.map(_.rdata).reverse)
278  intrMod.io.in.hsiprios := Cat(siregiprios.map(_.rdata).reverse)
279  // val disableInterrupt = debugMode || (dcsr.rdata.STEP.asBool && !dcsr.rdata.STEPIE.asBool)
280  // val intrVec = Cat(debugIntr && !debugMode, mie.rdata.asUInt(11, 0) & mip.rdata.asUInt & intrVecEnable.asUInt) // Todo: asUInt(11,0) is ok?
281
282  val intrVec = RegEnable(intrMod.io.out.interruptVec.bits, 0.U, intrMod.io.out.interruptVec.valid)
283
284  val trapHandleMod = Module(new TrapHandleModule)
285
286  trapHandleMod.io.in.trapInfo.valid := hasTrap
287  trapHandleMod.io.in.trapInfo.bits.trapVec := trapVec.asUInt
288  trapHandleMod.io.in.trapInfo.bits.intrVec := intrVec
289  trapHandleMod.io.in.trapInfo.bits.isInterrupt := trapIsInterrupt
290  trapHandleMod.io.in.privState := privState
291  trapHandleMod.io.in.mideleg := mideleg.regOut
292  trapHandleMod.io.in.medeleg := medeleg.regOut
293  trapHandleMod.io.in.hideleg := hideleg.regOut
294  trapHandleMod.io.in.hedeleg := hedeleg.regOut
295  trapHandleMod.io.in.mtvec := mtvec.regOut
296  trapHandleMod.io.in.stvec := stvec.regOut
297  trapHandleMod.io.in.vstvec := vstvec.regOut
298
299  val entryPrivState = trapHandleMod.io.out.entryPrivState
300
301  // PMP
302  val pmpEntryMod = Module(new PMPEntryHandleModule)
303  pmpEntryMod.io.in.pmpCfg  := cfgs.map(_.regOut.asInstanceOf[PMPCfgBundle])
304  pmpEntryMod.io.in.pmpAddr := pmpaddr.map(_.regOut.asInstanceOf[PMPAddrBundle])
305  pmpEntryMod.io.in.ren   := ren
306  pmpEntryMod.io.in.wen   := wen
307  pmpEntryMod.io.in.addr  := addr
308  pmpEntryMod.io.in.wdata := wdata
309
310  for ((id, (wBundle, _)) <- csrRwMap) {
311    if (vsMapS.contains(id)) {
312      // VS access CSR by S: privState.isModeVS && addrMappedToVS === sMapVS(id).U
313      wBundle.wen := wenLegal && ((isModeVS && addr === vsMapS(id).U) || (!isModeVS && addr === id.U))
314      wBundle.wdata := wdata
315    } else if (sMapVS.contains(id)) {
316      wBundle.wen := wenLegal && !isModeVS && addr === id.U
317      wBundle.wdata := wdata
318    } else {
319      wBundle.wen := wenLegal && addr === id.U
320      wBundle.wdata := wdata
321    }
322  }
323
324  // Todo: support set dirty only when fcsr has changed
325  private val writeFpState = wenLegal && Seq(CSRs.fflags, CSRs.frm, CSRs.fcsr).map(_.U === addr).reduce(_ || _)
326  private val writeVecState = wenLegal && Seq(CSRs.vstart, CSRs.vxsat, CSRs.vxrm, CSRs.vcsr).map(_.U === addr).reduce(_ || _)
327
328  permitMod.io.in.csrAccess.ren := ren
329  permitMod.io.in.csrAccess.wen := wen
330  permitMod.io.in.csrAccess.addr := addr
331
332  permitMod.io.in.privState := privState
333  permitMod.io.in.debugMode := debugMode
334
335  permitMod.io.in.mret := io.mret
336  permitMod.io.in.sret := io.sret
337  permitMod.io.in.wfi  := io.wfi
338  permitMod.io.in.csrIsCustom := customCSRMods.map(_.addr.U === addr).reduce(_ || _).orR
339
340  permitMod.io.in.status.tsr := mstatus.regOut.TSR.asBool
341  permitMod.io.in.status.vtsr := hstatus.regOut.VTSR.asBool
342
343  permitMod.io.in.status.tw := mstatus.regOut.TW.asBool
344  permitMod.io.in.status.vtw := hstatus.regOut.VTW.asBool
345
346  permitMod.io.in.status.tvm  := mstatus.regOut.TVM.asBool
347  permitMod.io.in.status.vtvm := hstatus.regOut.VTVM.asBool
348
349  miregiprios.foreach { mod =>
350    mod.w.wen := (addr === mireg.addr.U) && (miselect.regOut.ALL.asUInt === mod.addr.U)
351    mod.w.wdata := wdata
352  }
353
354  siregiprios.foreach { mod =>
355    mod.w.wen := (addr === sireg.addr.U) && (siselect.regOut.ALL.asUInt === mod.addr.U)
356    mod.w.wdata := wdata
357  }
358
359  mhartid.hartid := this.io.fromTop.hartId
360
361  cfgs.zipWithIndex.foreach { case (mod, i) =>
362    mod.w.wen := wen && (addr === (0x3A0 + i / 8 * 2).U)
363    mod.w.wdata := pmpEntryMod.io.out.pmpCfgWData(8*((i%8)+1)-1,8*(i%8))
364  }
365
366  pmpaddr.zipWithIndex.foreach{ case(mod, i) =>
367    mod.w.wen := wen && (addr === (0x3B0 + i).U)
368    mod.w.wdata := pmpEntryMod.io.out.pmpAddrWData(i)
369  }
370
371  csrMods.foreach { mod =>
372    mod match {
373      case m: HypervisorBundle =>
374        m.hstatus := hstatus.regOut
375        m.hvip := hvip.regOut
376        m.hideleg := hideleg.regOut
377        m.hedeleg := hedeleg.regOut
378        m.hgeip := hgeip.regOut
379        m.hgeie := hgeie.regOut
380        m.hip := hip.regOut
381        m.hie := hie.regOut
382      case _ =>
383    }
384    mod match {
385      case m: VirtualSupervisorBundle =>
386        m.v := V.asUInt.asBool
387      case _ =>
388    }
389    mod match {
390      case m: HasMachineInterruptBundle =>
391        m.mvien := mvien.regOut
392        m.mvip := mvip.regOut
393        m.mip := mip.regOut
394        m.mie := mie.regOut
395      case _ =>
396    }
397    mod match {
398      case m: HasMachineDelegBundle =>
399        m.mideleg := mideleg.regOut
400        m.medeleg := medeleg.regOut
401      case _ =>
402    }
403    mod match {
404      case m: HasMachineCounterControlBundle =>
405        m.mcountinhibit := mcountinhibit.regOut
406      case _ =>
407    }
408    mod match {
409      case m: HasExternalInterruptBundle =>
410        m.platformIRP := this.platformIRP
411      case _ =>
412    }
413    mod match {
414      case m: HasRobCommitBundle =>
415        m.robCommit := io.fromRob.commit
416        m.robCommit.fsDirty := io.fromRob.commit.fsDirty || writeFpState
417        m.robCommit.vsDirty := io.fromRob.commit.vsDirty || writeVecState
418      case _ =>
419    }
420    mod match {
421      case m: TrapEntryDEventSinkBundle =>
422        m.trapToD := trapEntryDEvent.out
423      case _ =>
424    }
425    mod match {
426      case m: TrapEntryMEventSinkBundle =>
427        m.trapToM := trapEntryMEvent.out
428      case _ =>
429    }
430    mod match {
431      case m: TrapEntryHSEventSinkBundle =>
432        m.trapToHS := trapEntryHSEvent.out
433      case _ =>
434    }
435    mod match {
436      case m: TrapEntryVSEventSinkBundle =>
437        m.trapToVS := trapEntryVSEvent.out
438      case _ =>
439    }
440    mod match {
441      case m: MretEventSinkBundle =>
442        m.retFromM := mretEvent.out
443      case _ =>
444    }
445    mod match {
446      case m: SretEventSinkBundle =>
447        m.retFromS := sretEvent.out
448      case _ =>
449    }
450    mod match {
451      case m: DretEventSinkBundle =>
452        m.retFromD := dretEvent.out
453      case _ =>
454    }
455    mod match {
456      case m: HasAIABundle =>
457        m.aiaToCSR.rdata.valid := fromAIA.rdata.valid
458        m.aiaToCSR.rdata.bits.data := fromAIA.rdata.bits.data
459        m.aiaToCSR.rdata.bits.illegal := fromAIA.rdata.bits.illegal
460        m.aiaToCSR.mtopei.valid := fromAIA.mtopei.valid
461        m.aiaToCSR.stopei.valid := fromAIA.stopei.valid
462        m.aiaToCSR.vstopei.valid := fromAIA.vstopei.valid
463        m.aiaToCSR.mtopei.bits := fromAIA.mtopei.bits
464        m.aiaToCSR.stopei.bits := fromAIA.stopei.bits
465        m.aiaToCSR.vstopei.bits := fromAIA.vstopei.bits
466      case _ =>
467    }
468    mod match {
469      case m: HasInterruptFilterSink =>
470        m.topIR.mtopi  := intrMod.io.out.mtopi
471        m.topIR.stopi  := intrMod.io.out.stopi
472        m.topIR.vstopi := intrMod.io.out.vstopi
473      case _ =>
474    }
475    mod match {
476      case m: HasISelectBundle =>
477        m.privState := privState
478        m.miselect := miselect.regOut
479        m.siselect := siselect.regOut
480        m.mireg := mireg.regOut.asUInt
481        m.sireg := sireg.regOut.asUInt
482      case _ =>
483    }
484    mod match {
485      case m: HasPMPAddrSink =>
486        m.addrRData := pmpEntryMod.io.out.pmpAddrRData
487      case _ =>
488    }
489  }
490
491  csrMods.foreach { mod =>
492    println(s"${mod.modName}: ")
493    println(mod.dumpFields)
494  }
495
496  trapEntryMEvent .valid := hasTrap && entryPrivState.isModeM
497  trapEntryHSEvent.valid := hasTrap && entryPrivState.isModeHS
498  trapEntryVSEvent.valid := hasTrap && entryPrivState.isModeVS
499
500  Seq(trapEntryMEvent, trapEntryHSEvent, trapEntryVSEvent, trapEntryDEvent).foreach { eMod =>
501    eMod.in match {
502      case in: TrapEntryEventInput =>
503        in.causeNO := trapHandleMod.io.out.causeNO
504        in.trapPc := trapPC
505        in.isCrossPageIPF := trapIsCrossPageIPF
506
507        in.iMode.PRVM := PRVM
508        in.iMode.V := V
509        in.dMode.PRVM := Mux(mstatus.regOut.MPRV.asBool, mstatus.regOut.MPP, PRVM)
510        in.dMode.V := Mux(mstatus.regOut.MPRV.asBool, mstatus.regOut.MPV, V)
511
512        in.privState := privState
513        in.mstatus := mstatus.regOut
514        in.hstatus := hstatus.regOut
515        in.sstatus := mstatus.sstatus
516        in.vsstatus := vsstatus.regOut
517        in.pcFromXtvec := trapHandleMod.io.out.pcFromXtvec
518
519        in.satp  := satp.regOut
520        in.vsatp := vsatp.regOut
521        in.hgatp := hgatp.regOut
522
523        in.memExceptionVAddr := io.fromMem.excpVA
524        in.memExceptionGPAddr := io.fromMem.excpGPA
525    }
526  }
527
528  mretEvent.valid := legalMret
529  mretEvent.in match {
530    case in =>
531      in.mstatus := mstatus.regOut
532      in.mepc := mepc.regOut
533  }
534
535  sretEvent.valid := legalSret
536  sretEvent.in match {
537    case in =>
538      in.privState := privState
539      in.sstatus := mstatus.sstatus
540      in.hstatus := hstatus.regOut
541      in.vsstatus := vsstatus.regOut
542      in.sepc := sepc.regOut
543      in.vsepc := vsepc.regOut
544  }
545
546  dretEvent.valid := isDret
547  dretEvent.in match {
548    case in =>
549      in.dcsr := dcsr.regOut
550      in.dpc  := dpc.regOut
551      in.mstatus := mstatus.regOut
552  }
553
554  PRVM := MuxCase(
555    PRVM,
556    events.filter(_.out.isInstanceOf[EventUpdatePrivStateOutput]).map {
557      x => x.out match {
558        case xx: EventUpdatePrivStateOutput => (xx.privState.valid -> xx.privState.bits.PRVM)
559      }
560    }
561  )
562
563  V := MuxCase(
564    V,
565    events.filter(_.out.isInstanceOf[EventUpdatePrivStateOutput]).map {
566      x => x.out match {
567        case xx: EventUpdatePrivStateOutput => (xx.privState.valid -> xx.privState.bits.V)
568      }
569    }
570  )
571
572  debugMode := MuxCase(
573    debugMode,
574    Seq(
575      dretEvent.out.debugMode.valid -> dretEvent.out.debugMode.bits,
576      trapEntryDEvent.out.debugMode.valid -> trapEntryDEvent.out.debugMode.bits
577    )
578  )
579
580  debugIntrEnable := MuxCase(
581    debugIntrEnable,
582    Seq(
583      dretEvent.out.debugIntrEnable.valid -> dretEvent.out.debugIntrEnable.bits,
584      trapEntryDEvent.out.debugIntrEnable.valid -> trapEntryDEvent.out.debugIntrEnable.bits
585    )
586  )
587
588  // perf
589  val addrInPerfCnt = (addr >= CSRs.mcycle.U) && (addr <= CSRs.mhpmcounter31.U) ||
590    (addr >= mcountinhibit.addr.U) && (addr <= mhpmevents.last.addr.U) ||
591    (addr >= CSRs.cycle.U) && (addr <= CSRs.hpmcounter31.U) ||
592    (addr === CSRs.mip.U) ||
593    (addr === CSRs.hip.U) ||
594    Cat(aiaCSRMap.keys.toSeq.sorted.map(_.U === addr)).orR ||
595    (addr === CSRs.stimecmp.U) ||
596    (addr === CSRs.mcounteren.U) ||
597    (addr === CSRs.scounteren.U) ||
598    (addr === CSRs.menvcfg.U)
599  // Todo: may be vsip and sip
600
601  // flush
602  val resetSatp = Cat(Seq(satp, vsatp, hgatp).map(_.addr.U === addr)).orR && wenLegal // write to satp will cause the pipeline be flushed
603
604  val wFcsrChangeRM = addr === fcsr.addr.U && wenLegal && wdata(7, 5) =/= fcsr.frm
605  val wFrmChangeRM  = addr === CSRs.frm.U  && wenLegal && wdata(2, 0) =/= fcsr.frm
606  val frmChange = wFcsrChangeRM || wFrmChangeRM
607
608  val wVcsrChangeRM = addr === CSRs.vcsr.U && wenLegal && wdata(2, 1) =/= vcsr.vxrm
609  val wVxrmChangeRM = addr === CSRs.vxrm.U && wenLegal && wdata(1, 0) =/= vcsr.vxrm
610  val vxrmChange = wVcsrChangeRM || wVxrmChangeRM
611
612  val triggerFrontendChange = Wire(Bool())
613  val flushPipe = resetSatp || frmChange || vxrmChange || triggerFrontendChange
614
615  // fence
616  val tvm = mstatus.regOut.TVM.asBool
617  val vtvm = hstatus.regOut.VTVM.asBool
618
619  private val rdata = Mux1H(csrRwMap.map { case (id, (_, rBundle)) =>
620    (raddr === id.U) -> rBundle.asUInt
621  })
622
623  private val regOut = Mux1H(csrOutMap.map { case (id, regOut) =>
624    (raddr === id.U) -> regOut
625  })
626
627  private val needTargetUpdate = mretEvent.out.targetPc.valid || sretEvent.out.targetPc.valid || dretEvent.out.targetPc.valid ||
628    trapEntryMEvent.out.targetPc.valid || trapEntryHSEvent.out.targetPc.valid || trapEntryVSEvent.out.targetPc.valid || trapEntryDEvent.out.targetPc.valid
629
630  private val noCSRIllegal = (ren || wen) && Cat(csrRwMap.keys.toSeq.sorted.map(csrAddr => !(addr === csrAddr.U))).andR
631
632  io.out.EX_II := permitMod.io.out.EX_II || noCSRIllegal
633  io.out.EX_VI := permitMod.io.out.EX_VI
634  io.out.flushPipe := flushPipe
635
636  io.out.rData := Mux(ren, rdata, 0.U)
637  io.out.regOut := regOut
638  io.out.targetPc := DataHoldBypass(
639    Mux(trapEntryDEvent.out.targetPc.valid,
640      trapEntryDEvent.out.targetPc.bits,
641      Mux1H(Seq(
642        mretEvent.out.targetPc.valid -> mretEvent.out.targetPc.bits,
643        sretEvent.out.targetPc.valid -> sretEvent.out.targetPc.bits,
644        dretEvent.out.targetPc.valid -> dretEvent.out.targetPc.bits,
645        trapEntryMEvent.out.targetPc.valid -> trapEntryMEvent.out.targetPc.bits,
646        trapEntryHSEvent.out.targetPc.valid -> trapEntryHSEvent.out.targetPc.bits,
647        trapEntryVSEvent.out.targetPc.valid -> trapEntryVSEvent.out.targetPc.bits)
648      )
649    ),
650  needTargetUpdate)
651
652  io.out.privState := privState
653
654  io.out.fpState.frm := fcsr.frm
655  io.out.fpState.off := mstatus.regOut.FS === ContextStatus.Off
656  io.out.vecState.vstart := vstart.rdata.asUInt
657  io.out.vecState.vxsat := vcsr.vxsat
658  io.out.vecState.vxrm := vcsr.vxrm
659  io.out.vecState.vcsr := vcsr.rdata.asUInt
660  io.out.vecState.vl := vl.rdata.asUInt
661  io.out.vecState.vtype := vtype.rdata.asUInt // Todo: check correct
662  io.out.vecState.vlenb := vlenb.rdata.asUInt
663  io.out.vecState.off := mstatus.regOut.VS === ContextStatus.Off
664  io.out.isPerfCnt := addrInPerfCnt
665  io.out.interrupt := intrMod.io.out.interruptVec.valid
666  io.out.wfiEvent := debugIntr || (mie.rdata.asUInt & mip.rdata.asUInt).orR
667  io.out.debugMode := debugMode
668  io.out.singleStepFlag := !debugMode && dcsr.regOut.STEP
669  io.out.tvm := tvm
670  io.out.vtvm := vtvm
671
672  /**
673   * debug_begin
674   */
675  // debug_intr
676  val hasIntr = hasTrap && trapIsInterrupt
677  val hasDebugIntr = hasIntr && intrVec(CSRConst.IRQ_DEBUG)
678
679  // debug_exception_ebreak
680  val hasExp = hasTrap && !trapIsInterrupt
681  val breakPoint = trapVec(ExceptionNO.breakPoint).asBool
682  val hasBreakPoint = hasExp && breakPoint
683  val ebreakEnterDebugMode =
684    (privState.isModeM && dcsr.regOut.EBREAKM.asBool) ||
685      (privState.isModeHS && dcsr.regOut.EBREAKS.asBool) ||
686      (privState.isModeHU && dcsr.regOut.EBREAKU.asBool)
687  val hasDebugEbreakException = hasBreakPoint && ebreakEnterDebugMode
688
689  // debug_exception_trigger
690  val triggerFrontendHitVec = triggerCf.frontendHit
691  val triggerMemHitVec = triggerCf.backendHit
692  val triggerHitVec = triggerFrontendHitVec.asUInt | triggerMemHitVec.asUInt // Todo: update mcontrol.hit
693  val triggerFrontendCanFireVec = triggerCf.frontendCanFire.asUInt
694  val triggerMemCanFireVec = triggerCf.backendCanFire.asUInt
695  val triggerCanFireVec = triggerFrontendCanFireVec | triggerMemCanFireVec
696  val tdata1WireVec = tdata1RegVec.map{ mod => {
697      val tdata1Wire = Wire(new Tdata1Bundle)
698      tdata1Wire := mod.rdata
699      tdata1Wire
700  }}
701  val tdata2WireVec = tdata2RegVec.map{ mod => {
702      val tdata2Wire = Wire(new Tdata2Bundle)
703      tdata2Wire := mod.rdata
704      tdata2Wire
705  }}
706  val mcontrolWireVec = tdata1WireVec.map{ mod => {
707    val mcontrolWire = Wire(new Mcontrol)
708    mcontrolWire := mod.DATA.asUInt
709    mcontrolWire
710  }}
711
712  // More than one triggers can hit at the same time, but only fire one
713  // We select the first hit trigger to fire
714  val triggerFireOH = PriorityEncoderOH(triggerCanFireVec)
715  val triggerFireAction = PriorityMux(triggerFireOH, tdata1WireVec.map(_.getTriggerAction)).asUInt
716  val hasTriggerFire = hasExp && triggerCf.canFire
717  val hasDebugTriggerException = hasTriggerFire && (triggerFireAction === TrigAction.DebugMode.asUInt)
718
719  // debug_exception_single
720  val hasSingleStep = hasExp && io.fromRob.trap.bits.singleStep
721
722  val hasDebugException = hasDebugEbreakException || hasDebugTriggerException || hasSingleStep
723  val hasDebugTrap = hasDebugException || hasDebugIntr
724
725  trapEntryDEvent.valid                       := hasDebugTrap && !debugMode
726  trapEntryDEvent.in.hasDebugIntr             := hasDebugIntr
727  trapEntryDEvent.in.debugMode                := debugMode
728  trapEntryDEvent.in.hasTrap                  := hasTrap
729  trapEntryDEvent.in.hasSingleStep            := hasSingleStep
730  trapEntryDEvent.in.hasTriggerFire           := hasTriggerFire
731  trapEntryDEvent.in.hasDebugEbreakException  := hasDebugEbreakException
732  trapEntryDEvent.in.breakPoint               := breakPoint
733
734  trapHandleMod.io.in.trapInfo.bits.singleStep  := hasSingleStep
735  trapHandleMod.io.in.trapInfo.bits.triggerFire := hasTriggerFire
736
737  intrMod.io.in.debugMode := debugMode
738  intrMod.io.in.debugIntr := debugIntr
739  intrMod.io.in.dcsr      := dcsr.rdata.asUInt
740
741  val tselect1H = UIntToOH(tselect.rdata.asUInt, TriggerNum).asBools
742  val chainVec = mcontrolWireVec.map(_.CHAIN.asBool)
743  val newTriggerChainVec = tselect1H.zip(chainVec).map{case(a, b) => a | b}
744  val newTriggerChainIsLegal = TriggerUtil.TriggerCheckChainLegal(newTriggerChainVec, TriggerChainMaxLength)
745
746  val tdata1Update  = addr === tdata1.addr.U && wenLegal
747  val tdata2Update  = addr === tdata2.addr.U && wenLegal
748  val triggerUpdate = tdata1Update || tdata2Update
749
750  tdata1RegVec.foreach { mod =>
751    mod match {
752      case m: HasdebugModeBundle =>
753        m.debugMode := debugMode
754        m.chainable := newTriggerChainIsLegal
755      case _ =>
756    }
757  }
758  tdata1RegVec.zip(tdata2RegVec).zipWithIndex.map { case ((mod1, mod2), idx) => {
759      mod1.w.wen    := tdata1Update && (tselect.rdata === idx.U)
760      mod1.w.wdata  := wdata
761      mod2.w.wen    := tdata2Update && (tselect.rdata === idx.U)
762      mod2.w.wdata  := wdata
763    }
764  }
765
766  val tdata1Wdata = Wire(new Tdata1Bundle)
767  tdata1Wdata := wdata
768  val mcontrolWdata = Wire(new Mcontrol)
769  mcontrolWdata := tdata1Wdata.DATA.asUInt
770  val tdata1TypeWdata = tdata1Wdata.TYPE
771
772  val tdata1Selected = Wire(new Tdata1Bundle)
773  tdata1Selected := tdata1.rdata.asUInt
774  val mcontrolSelected = Wire(new Mcontrol)
775  mcontrolSelected := tdata1Selected.DATA.asUInt
776  val tdata2Selected = Wire(new Tdata2Bundle)
777  tdata2Selected := tdata2.rdata.asUInt
778
779  val frontendTriggerUpdate =
780    tdata1Update && tdata1TypeWdata.isLegal && mcontrolWdata.isFetchTrigger ||
781      mcontrolSelected.isFetchTrigger && triggerUpdate
782
783  val memTriggerUpdate =
784    tdata1Update && tdata1TypeWdata.isLegal && mcontrolWdata.isMemAccTrigger ||
785      mcontrolSelected.isMemAccTrigger && triggerUpdate
786
787  val triggerEnableVec = tdata1WireVec.zip(mcontrolWireVec).map { case(tdata1, mcontrol) =>
788    tdata1.TYPE.isLegal && (
789      mcontrol.M && privState.isModeM ||
790        mcontrol.S && (privState.isModeHS) ||
791        mcontrol.U && privState.isModeHU)
792  }
793
794  val fetchTriggerEnableVec = triggerEnableVec.zip(mcontrolWireVec).map {
795    case (tEnable, mod) => tEnable && mod.isFetchTrigger
796  }
797  val memAccTriggerEnableVec = triggerEnableVec.zip(mcontrolWireVec).map {
798    case (tEnable, mod) => tEnable && mod.isMemAccTrigger
799  }
800
801  triggerFrontendChange := frontendTriggerUpdate
802
803  io.out.frontendTrigger.tUpdate.valid       := RegNext(RegNext(frontendTriggerUpdate))
804  io.out.frontendTrigger.tUpdate.bits.addr   := tselect.rdata.asUInt
805  io.out.frontendTrigger.tUpdate.bits.tdata.GenTdataDistribute(tdata1Selected, tdata2Selected)
806  io.out.frontendTrigger.tEnableVec          := fetchTriggerEnableVec
807  io.out.memTrigger.tUpdate.valid            := RegNext(RegNext(memTriggerUpdate))
808  io.out.memTrigger.tUpdate.bits.addr        := tselect.rdata.asUInt
809  io.out.memTrigger.tUpdate.bits.tdata.GenTdataDistribute(tdata1Selected, tdata2Selected)
810  io.out.memTrigger.tEnableVec               := memAccTriggerEnableVec
811  /**
812   * debug_end
813   */
814
815  /**
816   * [[io.out.custom]] connection
817   */
818  io.out.custom.l1I_pf_enable           := spfctl.regOut.L1I_PF_ENABLE.asBool
819  io.out.custom.l2_pf_enable            := spfctl.regOut.L2_PF_ENABLE.asBool
820  io.out.custom.l1D_pf_enable           := spfctl.regOut.L1D_PF_ENABLE.asBool
821  io.out.custom.l1D_pf_train_on_hit     := spfctl.regOut.L1D_PF_TRAIN_ON_HIT.asBool
822  io.out.custom.l1D_pf_enable_agt       := spfctl.regOut.L1D_PF_ENABLE_AGT.asBool
823  io.out.custom.l1D_pf_enable_pht       := spfctl.regOut.L1D_PF_ENABLE_PHT.asBool
824  io.out.custom.l1D_pf_active_threshold := spfctl.regOut.L1D_PF_ACTIVE_THRESHOLD.asUInt
825  io.out.custom.l1D_pf_active_stride    := spfctl.regOut.L1D_PF_ACTIVE_STRIDE.asUInt
826  io.out.custom.l1D_pf_enable_stride    := spfctl.regOut.L1D_PF_ENABLE_STRIDE.asBool
827  io.out.custom.l2_pf_store_only        := spfctl.regOut.L2_PF_STORE_ONLY.asBool
828
829  io.out.custom.icache_parity_enable    := sfetchctl.regOut.ICACHE_PARITY_ENABLE.asBool
830
831  io.out.custom.lvpred_disable          := slvpredctl.regOut.LVPRED_DISABLE.asBool
832  io.out.custom.no_spec_load            := slvpredctl.regOut.NO_SPEC_LOAD.asBool
833  io.out.custom.storeset_wait_store     := slvpredctl.regOut.STORESET_WAIT_STORE.asBool
834  io.out.custom.storeset_no_fast_wakeup := slvpredctl.regOut.STORESET_NO_FAST_WAKEUP.asBool
835  io.out.custom.lvpred_timeout          := slvpredctl.regOut.LVPRED_TIMEOUT.asUInt
836
837  io.out.custom.bp_ctrl.ubtb_enable     := sbpctl.regOut.UBTB_ENABLE .asBool
838  io.out.custom.bp_ctrl.btb_enable      := sbpctl.regOut.BTB_ENABLE  .asBool
839  io.out.custom.bp_ctrl.bim_enable      := sbpctl.regOut.BIM_ENABLE  .asBool
840  io.out.custom.bp_ctrl.tage_enable     := sbpctl.regOut.TAGE_ENABLE .asBool
841  io.out.custom.bp_ctrl.sc_enable       := sbpctl.regOut.SC_ENABLE   .asBool
842  io.out.custom.bp_ctrl.ras_enable      := sbpctl.regOut.RAS_ENABLE  .asBool
843  io.out.custom.bp_ctrl.loop_enable     := sbpctl.regOut.LOOP_ENABLE .asBool
844
845  io.out.custom.sbuffer_threshold                := smblockctl.regOut.SBUFFER_THRESHOLD.asUInt
846  io.out.custom.ldld_vio_check_enable            := smblockctl.regOut.LDLD_VIO_CHECK_ENABLE.asBool
847  io.out.custom.soft_prefetch_enable             := smblockctl.regOut.SOFT_PREFETCH_ENABLE.asBool
848  io.out.custom.cache_error_enable               := smblockctl.regOut.CACHE_ERROR_ENABLE.asBool
849  io.out.custom.uncache_write_outstanding_enable := smblockctl.regOut.UNCACHE_WRITE_OUTSTANDING_ENABLE.asBool
850
851  io.out.custom.fusion_enable           := srnctl.regOut.FUSION_ENABLE.asBool
852  io.out.custom.wfi_enable              := srnctl.regOut.WFI_ENABLE.asBool
853
854  // Todo: record the last address to avoid xireg is different with xiselect
855  toAIA.addr.valid := wenLegal && Seq(miselect, siselect, vsiselect).map(
856    _.addr.U === addr
857  ).reduce(_ || _)
858  toAIA.addr.bits.addr := addr
859  toAIA.addr.bits.prvm := PRVM
860  toAIA.addr.bits.v := V
861  toAIA.vgein := hstatus.regOut.VGEIN.asUInt
862  toAIA.wdata.valid := wenLegal && Seq(mireg, sireg, vsireg).map(
863    _.addr.U === addr
864  ).reduce(_ || _)
865  toAIA.wdata.bits.data := wdata
866  toAIA.mClaim := wenLegal && mtopei.addr.U === addr
867  toAIA.sClaim := wenLegal && stopei.addr.U === addr
868  toAIA.vsClaim := wenLegal && vstopei.addr.U === addr
869
870  // tlb
871  io.tlb.satpASIDChanged  := wenLegal && addr === CSRs. satp.U && satp .regOut.ASID =/= wdata.asTypeOf(new SatpBundle).ASID
872  io.tlb.vsatpASIDChanged := wenLegal && addr === CSRs.vsatp.U && vsatp.regOut.ASID =/= wdata.asTypeOf(new SatpBundle).ASID
873  io.tlb.hgatpVMIDChanged := wenLegal && addr === CSRs.hgatp.U && hgatp.regOut.VMID =/= wdata.asTypeOf(new HgatpBundle).VMID
874  io.tlb.satp := satp.rdata
875  io.tlb.vsatp := vsatp.rdata
876  io.tlb.hgatp := hgatp.rdata
877  io.tlb.mxr  :=  mstatus.regOut.MXR.asBool
878  io.tlb.sum  :=  mstatus.regOut.SUM.asBool
879  io.tlb.vmxr := vsstatus.regOut.MXR.asBool
880  io.tlb.vsum := vsstatus.regOut.SUM.asBool
881  io.tlb.spvp :=  hstatus.regOut.SPVP.asBool
882
883  io.tlb.imode := PRVM.asUInt
884  io.tlb.dmode := Mux((debugMode && dcsr.regOut.MPRVEN.asBool || !debugMode) && mstatus.regOut.MPRV.asBool, mstatus.regOut.MPP.asUInt, PRVM.asUInt)
885
886  io.toDecode.illegalInst.sfenceVMA  := isModeHS && mstatus.regOut.TVM  || isModeHU
887  io.toDecode.virtualInst.sfenceVMA  := isModeVS && hstatus.regOut.VTVM || isModeVU
888  io.toDecode.illegalInst.sfencePart := isModeHU
889  io.toDecode.virtualInst.sfencePart := isModeVU
890  io.toDecode.illegalInst.hfenceGVMA := isModeHS && mstatus.regOut.TVM || isModeHU
891  io.toDecode.illegalInst.hfenceVVMA := isModeHU
892  io.toDecode.virtualInst.hfence     := isModeVS || isModeVU
893  io.toDecode.illegalInst.hlsv       := isModeHU && hstatus.regOut.HU
894  io.toDecode.virtualInst.hlsv       := isModeVS || isModeVU
895  io.toDecode.illegalInst.fsIsOff    := mstatus.regOut.FS === ContextStatus.Off
896  io.toDecode.illegalInst.vsIsOff    := mstatus.regOut.VS === ContextStatus.Off
897
898  // Always instantiate basic difftest modules.
899  if (env.AlwaysBasicDiff || env.EnableDifftest) {
900    val hartId = io.fromTop.hartId
901    val trapValid = io.fromRob.trap.valid
902    val trapNO = trapHandleMod.io.out.causeNO.ExceptionCode.asUInt
903    val interrupt = trapHandleMod.io.out.causeNO.Interrupt.asBool
904    val interruptNO = Mux(interrupt, trapNO, 0.U)
905    val exceptionNO = Mux(!interrupt, trapNO, 0.U)
906    val ivmHS = isModeHS &&  satp.regOut.MODE =/= SatpMode.Bare
907    val ivmVS = isModeVS && vsatp.regOut.MODE =/= SatpMode.Bare
908    // When enable virtual memory, the higher bit should fill with the msb of address of Sv39/Sv48/Sv57
909    val exceptionPC = Mux(ivmHS || ivmVS, SignExt(trapPC, XLEN), ZeroExt(trapPC, XLEN))
910
911    val diffArchEvent = DifftestModule(new DiffArchEvent, delay = 3, dontCare = true)
912    diffArchEvent.coreid := hartId
913    diffArchEvent.valid := trapValid
914    diffArchEvent.interrupt := interruptNO
915    diffArchEvent.exception := exceptionNO
916    diffArchEvent.exceptionPC := exceptionPC
917    if (env.EnableDifftest) {
918      diffArchEvent.exceptionInst := io.fromRob.trap.bits.instr
919    }
920
921    val diffCSRState = DifftestModule(new DiffCSRState)
922    diffCSRState.coreid         := hartId
923    diffCSRState.privilegeMode  := privState.PRVM.asUInt
924    diffCSRState.mstatus        := mstatus.rdata.asUInt
925    diffCSRState.sstatus        := mstatus.sstatus.asUInt
926    diffCSRState.mepc           := mepc.rdata.asUInt
927    diffCSRState.sepc           := sepc.rdata.asUInt
928    diffCSRState.mtval          := mtval.rdata.asUInt
929    diffCSRState.stval          := stval.rdata.asUInt
930    diffCSRState.mtvec          := mtvec.rdata.asUInt
931    diffCSRState.stvec          := stvec.rdata.asUInt
932    diffCSRState.mcause         := mcause.rdata.asUInt
933    diffCSRState.scause         := scause.rdata.asUInt
934    diffCSRState.satp           := satp.rdata.asUInt
935    diffCSRState.mip            := mip.regOut.asUInt
936    diffCSRState.mie            := mie.rdata.asUInt
937    diffCSRState.mscratch       := mscratch.rdata.asUInt
938    diffCSRState.sscratch       := sscratch.rdata.asUInt
939    diffCSRState.mideleg        := mideleg.rdata.asUInt
940    diffCSRState.medeleg        := medeleg.rdata.asUInt
941
942    val diffDebugMode = DifftestModule(new DiffDebugMode)
943    diffDebugMode.coreid    := hartId
944    diffDebugMode.debugMode := debugMode
945    diffDebugMode.dcsr      := dcsr.rdata.asUInt
946    diffDebugMode.dpc       := dpc.rdata.asUInt
947    diffDebugMode.dscratch0 := dscratch0.rdata.asUInt
948    diffDebugMode.dscratch1 := dscratch1.rdata.asUInt
949
950    val diffVecCSRState = DifftestModule(new DiffVecCSRState)
951    diffVecCSRState.coreid := hartId
952    diffVecCSRState.vstart := vstart.rdata.asUInt
953    diffVecCSRState.vxsat := vcsr.vxsat.asUInt
954    diffVecCSRState.vxrm := vcsr.vxrm.asUInt
955    diffVecCSRState.vcsr := vcsr.rdata.asUInt
956    diffVecCSRState.vl := vl.rdata.asUInt
957    diffVecCSRState.vtype := vtype.rdata.asUInt
958    diffVecCSRState.vlenb := vlenb.rdata.asUInt
959
960    val diffHCSRState = DifftestModule(new DiffHCSRState)
961    diffHCSRState.coreid      := hartId
962    diffHCSRState.virtMode    := privState.V.asBool
963    diffHCSRState.mtval2      := mtval2.rdata.asUInt
964    diffHCSRState.mtinst      := mtinst.rdata.asUInt
965    diffHCSRState.hstatus     := hstatus.rdata.asUInt
966    diffHCSRState.hideleg     := hideleg.rdata.asUInt
967    diffHCSRState.hedeleg     := hedeleg.rdata.asUInt
968    diffHCSRState.hcounteren  := hcounteren.rdata.asUInt
969    diffHCSRState.htval       := htval.rdata.asUInt
970    diffHCSRState.htinst      := htinst.rdata.asUInt
971    diffHCSRState.hgatp       := hgatp.rdata.asUInt
972    diffHCSRState.vsstatus    := vsstatus.rdata.asUInt
973    diffHCSRState.vstvec      := vstvec.rdata.asUInt
974    diffHCSRState.vsepc       := vsepc.rdata.asUInt
975    diffHCSRState.vscause     := vscause.rdata.asUInt
976    diffHCSRState.vstval      := vstval.rdata.asUInt
977    diffHCSRState.vsatp       := vsatp.rdata.asUInt
978    diffHCSRState.vsscratch   := vsscratch.rdata.asUInt
979
980  }
981}
982
983trait SupervisorMachineAliasConnect { self: NewCSR with MachineLevel with SupervisorLevel =>
984  mip.fromMvip := mvip.toMip
985  mip.fromSip := sip.toMip
986  mie.fromSie := sie.toMie
987}
988
989object NewCSRMain extends App {
990  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(
991    args :+ "--disable-always-basic-diff" :+ "--dump-fir" :+ "--fpga-platform" :+ "--target" :+ "verilog")
992
993  val defaultConfig = config.alterPartial({
994    // Get XSCoreParams and pass it to the "small module"
995    case XSCoreParamsKey => config(XSTileKey).head
996  })
997
998  Generator.execute(
999    firrtlOpts :+ "--full-stacktrace" :+ "--target-dir" :+ "backend",
1000    new NewCSR()(defaultConfig),
1001    firtoolOpts
1002  )
1003
1004  println("done")
1005}