xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala (revision 039cdc35f5f3b68b6295ec5ace90f22a77322e02) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import top.{ArgParser, Generator}
6import xiangshan.backend.fu.NewCSR.CSRDefines.{PrivMode, VirtMode}
7
8object CSRConfig {
9  final val GEILEN = 63
10
11  final val ASIDLEN = 16 // the length of ASID of XS implementation
12
13  final val ASIDMAX = 16 // the max value of ASIDLEN defined by spec
14
15  final val HIIDWidth = 12 // support Hvictl[27:16](IID)
16
17  final val VMIDLEN = 14 // the length of VMID of XS implementation
18
19  final val VMIDMAX = 14 // the max value of VMIDLEN defined by spec
20
21  final val VaddrWidth = 39 // only Sv39
22
23}
24
25class NewCSR extends Module
26  with MachineLevel
27  with SupervisorLevel
28  with HypervisorLevel
29  with VirtualSupervisorLevel
30  with Unprivileged
31  with HasExternalInterruptBundle
32  with HasInstCommitBundle
33  with SupervisorMachineAliasConnect {
34
35  val io = IO(new Bundle {
36    val w = Flipped(ValidIO(new Bundle {
37      val addr = UInt(12.W)
38      val data = UInt(64.W)
39    }))
40    val rAddr = Input(UInt(12.W))
41    val rData = Output(UInt(64.W))
42    val trap = Flipped(ValidIO(new Bundle {
43      val toPRVM = PrivMode()
44      val toV = VirtMode()
45    }))
46    val tret = Flipped(ValidIO(new Bundle {
47      val toPRVM = PrivMode()
48      val toV = VirtMode()
49    }))
50    // from interrupt controller
51    val fromIC = Input(new Bundle {
52      val vs = new CSRIRCBundle
53    })
54  })
55
56  val addr = io.w.bits.addr
57  val data = io.w.bits.data
58  val wen = io.w.valid
59
60  val PRVM = RegInit(PrivMode.M)
61  val V = RegInit(VirtMode.Off)
62
63  val trap = io.trap.valid
64  val trapToPRVM = io.trap.bits.toPRVM
65  val trapToV = io.trap.bits.toV
66  val trapToM = trapToPRVM === PrivMode.M
67  val trapToHS = trapToPRVM === PrivMode.S && trapToV === VirtMode.Off
68  val trapToHU = trapToPRVM === PrivMode.U && trapToV === VirtMode.Off
69  val trapToVS = trapToPRVM === PrivMode.S && trapToV === VirtMode.On
70  val trapToVU = trapToPRVM === PrivMode.U && trapToV === VirtMode.On
71
72  val tret = io.tret.valid
73  val tretPRVM = io.tret.bits.toPRVM
74  val tretV = io.tret.bits.toV
75  val isSret = tret && tretPRVM === PrivMode.S
76  val isMret = tret && tretPRVM === PrivMode.M
77
78  var csrRwMap = machineLevelCSRMap ++ supervisorLevelCSRMap ++ hypervisorCSRMap ++ virtualSupervisorCSRMap ++ unprivilegedCSRMap
79
80  val csrMods = machineLevelCSRMods ++ supervisorLevelCSRMods ++ hypervisorCSRMods ++ virtualSupervisorCSRMods ++ unprivilegedCSRMods
81
82  for ((id, (wBundle, _)) <- csrRwMap) {
83    wBundle.wen := wen && addr === id.U
84    wBundle.wdata := data
85  }
86  io.rData := Mux1H(csrRwMap.map { case (id, (_, rBundle)) =>
87    (io.rAddr === id.U) -> rBundle.asUInt
88  })
89
90  csrMods.foreach { mod =>
91    mod match {
92      case m: HypervisorBundle =>
93        m.hstatus := hstatus.regOut
94        m.hvip := hvip.regOut
95        m.hideleg := hideleg.regOut
96        m.hedeleg := hedeleg.regOut
97        m.hgeip := hgeip.regOut
98        m.hgeie := hgeie.regOut
99        m.hip := hip.regOut
100        m.hie := hie.regOut
101      case _ =>
102    }
103    mod match {
104      case m: HasMachineInterruptBundle =>
105        m.mvien := mvien.regOut
106        m.mvip := mvip.regOut
107        m.mip := mip.regOut
108        m.mie := mie.regOut
109      case _ =>
110    }
111    mod match {
112      case m: HasMachineDelegBundle =>
113        m.mideleg := mideleg.regOut
114        m.medeleg := medeleg.regOut
115      case _ =>
116    }
117    mod match {
118      case m: HasMachineCounterControlBundle =>
119        m.mcountinhibit := mcountinhibit.regOut
120      case _ =>
121    }
122    mod match {
123      case m: HasExternalInterruptBundle =>
124        m.platformIRP := this.platformIRP
125      case _ =>
126    }
127    mod match {
128      case m: HasInstCommitBundle =>
129        m.commitValid := this.commitValid
130        m.commitInstNum := this.commitInstNum
131      case _ =>
132    }
133  }
134
135  csrMods.foreach { mod =>
136    mod.commonIn.status := mstatus.mstatus
137    mod.commonIn.prvm := PRVM
138    mod.commonIn.v := V
139    mod.commonIn.hstatus := hstatus.rdata
140    println(s"${mod.modName}: ")
141    println(mod.dumpFields)
142  }
143}
144
145trait SupervisorMachineAliasConnect { self: NewCSR with MachineLevel with SupervisorLevel =>
146  mip.fromMvip := mvip.toMip
147  mip.fromSip := sip.toMip
148  mie.fromSie := sie.toMie
149}
150
151object NewCSRMain extends App {
152  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(
153    args :+ "--disable-always-basic-diff" :+ "--dump-fir" :+ "--fpga-platform" :+ "--target" :+ "verilog")
154
155  Generator.execute(
156    firrtlOpts :+ "--full-stacktrace" :+ "--target-dir" :+ "backend",
157    new NewCSR,
158    firtoolOpts
159  )
160
161  println("done")
162}