1package xiangshan.backend.fu.NewCSR 2 3import xiangshan.backend.fu.NewCSR.CSRDefines.{ 4 CSRRWField => RW, 5} 6 7class InterruptBundle extends CSRBundle { 8 // Software Interrupt 9 val SSI = RW(1) 10 val VSSI = RW(2) 11 val MSI = RW(3) 12 // Time Interrupt 13 val STI = RW(5) 14 val VSTI = RW(6) 15 val MTI = RW(7) 16 // External Interrupt 17 val SEI = RW(9) 18 val VSEI = RW(10) 19 val MEI = RW(11) 20 val SGEI = RW(12) 21 // SoC 22 val COI = RW(13) // Counter overflow interrupt 23 val LPRASEI = RW(35) // Low-priority RAS event interrupt 24 val HPRASEI = RW(43) // High-priority RAS event interrupt 25 26 def getVS = Seq(VSSI, VSTI, VSEI) 27 28 def getHS = Seq(SSI, STI, SEI) 29 30 def getM = Seq(MSI, MTI, MEI) 31 32 def getSOC = Seq(COI, LPRASEI, HPRASEI) 33 34 def getALL = Seq(SSI, VSSI, MSI, STI, VSTI, MTI, SEI, VSEI, MEI, SGEI, COI, LPRASEI, HPRASEI) 35} 36 37class InterruptPendingBundle extends CSRBundle { 38 // Software Interrupt 39 val SSIP = RW(1) 40 val VSSIP = RW(2) 41 val MSIP = RW(3) 42 // Time Interrupt 43 val STIP = RW(5) 44 val VSTIP = RW(6) 45 val MTIP = RW(7) 46 // External Interrupt 47 val SEIP = RW(9) 48 val VSEIP = RW(10) 49 val MEIP = RW(11) 50 val SGEIP = RW(12) 51 // SoC 52 val COIP = RW(13) // Counter overflow interrupt 53 val LPRASEIP = RW(35) // Low-priority RAS event interrupt 54 val HPRASEIP = RW(43) // High-priority RAS event interrupt 55 56 def getVS = Seq(VSSIP, VSTIP, VSEIP) 57 58 def getHS = Seq(SSIP, STIP, SEIP) 59 60 def getM = Seq(MSIP, MTIP, MEIP) 61 62 def getSOC = Seq(COIP, LPRASEIP, HPRASEIP) 63 64 def getALL = Seq(SSIP, VSSIP, MSIP, STIP, VSTIP, MTIP, SEIP, VSEIP, MEIP, SGEIP, COIP, LPRASEIP, HPRASEIP) 65} 66 67class InterruptEnableBundle extends CSRBundle { 68 // Software Interrupt 69 val SSIE = RW(1) 70 val VSSIE = RW(2) 71 val MSIE = RW(3) 72 // Time Interrupt 73 val STIE = RW(5) 74 val VSTIE = RW(6) 75 val MTIE = RW(7) 76 // External Interrupt 77 val SEIE = RW(9) 78 val VSEIE = RW(10) 79 val MEIE = RW(11) 80 val SGEIE = RW(12) 81 // SoC 82 val COIE = RW(13) // Counter overflow interrupt 83 val LPRASEIE = RW(35) // Low-priority RAS event interrupt 84 val HPRASEIE = RW(43) // High-priority RAS event interrupt 85 86 def getVS = Seq(VSSIE, VSTIE, VSEIE) 87 88 def getHS = Seq(SSIE, STIE, SEIE) 89 90 def getM = Seq(MSIE, MTIE, MEIE) 91 92 def getSOC = Seq(COIE, LPRASEIE, HPRASEIE) 93 94 def getALL = Seq(SSIE, VSSIE, MSIE, STIE, VSTIE, MTIE, SEIE, VSEIE, MEIE, SGEIE, COIE, LPRASEIE, HPRASEIE) 95} 96 97object InterruptNO { 98 // Software Interrupt 99 final val SSI = 1 100 final val VSSI = 2 101 final val MSI = 3 102 // Time Interrupt 103 final val STI = 5 104 final val VSTI = 6 105 final val MTI = 7 106 // External Interrupt 107 final val SEI = 9 108 final val VSEI = 10 109 final val MEI = 11 110 final val SGEI = 12 111 // SoC 112 final val COI = 13 113 final val LPRASEI = 35 114 final val HPRASEI = 43 115 116 val interruptDefaultPrio = Seq( 117 HPRASEI, 118 119 MEI, MSI, MTI, 120 SEI, SSI, STI, 121 SGEI, 122 VSEI, VSSI, VSTI, 123 COI, 124 125 LPRASEI 126 ) 127 128 def getPrioIdx(f: this.type => Int): Int = { 129 val idx = this.interruptDefaultPrio.indexOf(f(this)) 130 assert(idx != -1) 131 idx 132 } 133} 134