xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala (revision 8056933dbf3292e084aa2e583af87309f5811467) 
1package xiangshan.backend.fu.NewCSR
2
3import xiangshan.backend.fu.NewCSR.CSRDefines.{
4  CSRRWField => RW,
5}
6
7class InterruptBundle extends CSRBundle {
8  // Software Interrupt
9  val SSI      = RW(1)
10  val VSSI     = RW(2)
11  val MSI      = RW(3)
12  // Time Interrupt
13  val STI      = RW(5)
14  val VSTI     = RW(6)
15  val MTI      = RW(7)
16  // External Interrupt
17  val SEI      = RW(9)
18  val VSEI     = RW(10)
19  val MEI      = RW(11)
20  val SGEI     = RW(12)
21  // SoC
22  val COI      = RW(13) // Counter overflow interrupt
23  val LPRASEI  = RW(35) // Low-priority RAS event interrupt
24  val HPRASEI  = RW(43) // High-priority RAS event interrupt
25
26  def getVS = Seq(VSSI, VSTI, VSEI)
27
28  def getHS = Seq(SSI, STI, SEI)
29
30  def getM = Seq(MSI, MTI, MEI)
31
32  def getSOC = Seq(COI, LPRASEI, HPRASEI)
33}
34
35class InterruptPendingBundle extends CSRBundle {
36  // Software Interrupt
37  val SSIP     = RW(1)
38  val VSSIP    = RW(2)
39  val MSIP     = RW(3)
40  // Time Interrupt
41  val STIP     = RW(5)
42  val VSTIP    = RW(6)
43  val MTIP     = RW(7)
44  // External Interrupt
45  val SEIP     = RW(9)
46  val VSEIP    = RW(10)
47  val MEIP     = RW(11)
48  val SGEIP    = RW(12)
49  // SoC
50  val COIP     = RW(13) // Counter overflow interrupt
51  val LPRASEIP = RW(35) // Low-priority RAS event interrupt
52  val HPRASEIP = RW(43) // High-priority RAS event interrupt
53
54  def getVS = Seq(VSSIP, VSTIP, VSEIP)
55
56  def getHS = Seq(SSIP, STIP, SEIP)
57
58  def getM = Seq(MSIP, MTIP, MEIP)
59
60  def getSOC = Seq(COIP, LPRASEIP, HPRASEIP)
61
62  def getALL = Seq(SSIP, VSSIP, MSIP, STIP, VSTIP, MTIP, SEIP, VSEIP, MEIP, SGEIP, COIP, LPRASEIP, HPRASEIP)
63}
64
65class InterruptEnableBundle extends CSRBundle {
66  // Software Interrupt
67  val SSIE     = RW(1)
68  val VSSIE    = RW(2)
69  val MSIE     = RW(3)
70  // Time Interrupt
71  val STIE     = RW(5)
72  val VSTIE    = RW(6)
73  val MTIE     = RW(7)
74  // External Interrupt
75  val SEIE     = RW(9)
76  val VSEIE    = RW(10)
77  val MEIE     = RW(11)
78  val SGEIE    = RW(12)
79  // SoC
80  val COIE     = RW(13) // Counter overflow interrupt
81  val LPRASEIE = RW(35) // Low-priority RAS event interrupt
82  val HPRASEIE = RW(43) // High-priority RAS event interrupt
83
84  def getVS = Seq(VSSIE, VSTIE, VSEIE)
85
86  def getHS = Seq(SSIE, STIE, SEIE)
87
88  def getM = Seq(MSIE, MTIE, MEIE)
89
90  def getSOC = Seq(COIE, LPRASEIE, HPRASEIE)
91
92  def getALL = Seq(SSIE, VSSIE, MSIE, STIE, VSTIE, MTIE, SEIE, VSEIE, MEIE, SGEIE, COIE, LPRASEIE, HPRASEIE)
93}
94
95object InterruptNO {
96  // Software Interrupt
97  final val SSI  = 1
98  final val VSSI = 2
99  final val MSI  = 3
100  // Time Interrupt
101  final val STI  = 5
102  final val VSTI = 6
103  final val MTI  = 7
104  // External Interrupt
105  final val SEI  = 9
106  final val VSEI = 10
107  final val MEI  = 11
108  final val SGEI = 12
109  // SoC
110  final val COI = 13
111  final val LPRASEI = 35
112  final val HPRASEI = 43
113
114  val interruptDefaultPrio = Seq(
115    HPRASEI,
116
117    MEI, MSI, MTI,
118    SEI, SSI, STI,
119    SGEI,
120    VSEI, VSSI, VSTI,
121    COI,
122
123    LPRASEI
124  )
125
126  def getPrioIdx(f: this.type => Int): Int = {
127    val idx = this.interruptDefaultPrio.indexOf(f(this))
128    assert(idx != -1)
129    idx
130  }
131}
132