1075d4937Sjunxiong-jipackage xiangshan.backend.fu.NewCSR 2075d4937Sjunxiong-ji 3075d4937Sjunxiong-jiimport freechips.rocketchip.rocket.CSRs 4075d4937Sjunxiong-ji 5075d4937Sjunxiong-jiobject CSROoORead { 6075d4937Sjunxiong-ji /** 7075d4937Sjunxiong-ji * "Read only" CSRs that can be fully pipelined when read in CSRR instruction. 8075d4937Sjunxiong-ji * Only read by csr instructions. 9075d4937Sjunxiong-ji */ 10*8893eb2cSZhaoyang You val waitForwardInOrderCsrReadList = List( 11075d4937Sjunxiong-ji CSRs.fflags, 12075d4937Sjunxiong-ji CSRs.fcsr, 13075d4937Sjunxiong-ji CSRs.vxsat, 14075d4937Sjunxiong-ji CSRs.vcsr, 15075d4937Sjunxiong-ji CSRs.vstart, 16075d4937Sjunxiong-ji CSRs.sstatus, 17075d4937Sjunxiong-ji CSRs.vsstatus, 18075d4937Sjunxiong-ji CSRs.mstatus, 19075d4937Sjunxiong-ji CSRs.hstatus, 20075d4937Sjunxiong-ji CSRs.mnstatus, 21075d4937Sjunxiong-ji CSRs.dcsr, 22ef82825fSjunxiong-ji CSRs.vtype, 23*8893eb2cSZhaoyang You CSRs.mireg, 24*8893eb2cSZhaoyang You CSRs.sireg, 25*8893eb2cSZhaoyang You CSRs.vsireg, 26*8893eb2cSZhaoyang You ) 27*8893eb2cSZhaoyang You val blockBackwardInOrderCsrReadList = List( 28*8893eb2cSZhaoyang You CSRs.mireg, 29*8893eb2cSZhaoyang You CSRs.sireg, 30*8893eb2cSZhaoyang You CSRs.vsireg, 31075d4937Sjunxiong-ji ) 32075d4937Sjunxiong-ji} 33