1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import xiangshan.backend.fu.NewCSR.CSRConfig.VaddrMaxWidth 7import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, PrivMode, SatpMode, VirtMode} 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.AddrTransType 10 11 12class DretEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 13 val dcsr = ValidIO((new DcsrBundle).addInEvent(_.V, _.PRV)) 14 val mstatus = ValidIO((new MstatusBundle).addInEvent(_.MPRV)) 15 val debugMode = ValidIO(Bool()) 16 val debugIntrEnable = ValidIO(Bool()) 17 val targetPc = ValidIO(new TargetPCBundle) 18} 19 20class DretEventInput extends Bundle { 21 val dcsr = Input(new DcsrBundle) 22 val dpc = Input(new Epc) 23 val mstatus = Input(new MstatusBundle) 24 val satp = Input(new SatpBundle) 25 val vsatp = Input(new SatpBundle) 26 val hgatp = Input(new HgatpBundle) 27} 28 29class DretEventModule(implicit p: Parameters) extends Module with CSREventBase { 30 val in = IO(new DretEventInput) 31 val out = IO(new DretEventOutput) 32 33 private val satp = in.satp 34 private val vsatp = in.vsatp 35 private val hgatp = in.hgatp 36 private val nextPrivState = out.privState.bits 37 38 private val instrAddrTransType = AddrTransType( 39 bare = nextPrivState.isModeM || 40 (!nextPrivState.isVirtual && satp.MODE === SatpMode.Bare) || 41 (nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare), 42 sv39 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv39 || 43 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv39, 44 sv48 = !nextPrivState.isModeM && !nextPrivState.isVirtual && satp.MODE === SatpMode.Sv48 || 45 nextPrivState.isVirtual && vsatp.MODE === SatpMode.Sv48, 46 sv39x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4, 47 sv48x4 = nextPrivState.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4 48 ) 49 50 out := DontCare 51 52 out.debugMode.valid := valid 53 out.privState.valid := valid 54 out.dcsr.valid := valid 55 out.mstatus.valid := valid 56 out.debugIntrEnable.valid := valid 57 out.targetPc.valid := valid 58 59 out.privState.bits.PRVM := in.dcsr.PRV.asUInt 60 out.privState.bits.V := Mux(in.dcsr.PRV === PrivMode.M, VirtMode.Off.asUInt, in.dcsr.V.asUInt) 61 out.mstatus.bits.MPRV := Mux(!out.privState.bits.isModeM, 0.U, in.mstatus.MPRV.asUInt) 62 out.debugMode.bits := false.B 63 out.debugIntrEnable.bits := true.B 64 out.targetPc.bits.pc := in.dpc.asUInt 65 out.targetPc.bits.raiseIPF := instrAddrTransType.checkPageFault(in.dpc.asUInt) 66 out.targetPc.bits.raiseIAF := instrAddrTransType.checkAccessFault(in.dpc.asUInt) 67 out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.dpc.asUInt) 68} 69 70trait DretEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 71 val retFromD = IO(Flipped(new DretEventOutput)) 72 73 addUpdateBundleInCSREnumType(retFromD.getBundleByName(self.modName.toLowerCase())) 74 75 reconnectReg() 76} 77