xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala (revision c2a2229d405d725d960325a4a1899af7603d82af) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.HasXSParameter
8import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState}
9import xiangshan.backend.fu.NewCSR.CSRConfig._
10import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, SatpMode}
11import xiangshan.backend.fu.NewCSR._
12
13trait CSREvents { self: NewCSR =>
14  val trapEntryDEvent = Module(new TrapEntryDEventModule)
15
16  val trapEntryMEvent = Module(new TrapEntryMEventModule)
17
18  val trapEntryMNEvent = Module(new TrapEntryMNEventModule())
19
20  val trapEntryHSEvent = Module(new TrapEntryHSEventModule)
21
22  val trapEntryVSEvent = Module(new TrapEntryVSEventModule)
23
24  val mretEvent  = Module(new MretEventModule)
25
26  val mnretEvent = Module(new MNretEventModule)
27
28  val sretEvent  = Module(new SretEventModule)
29
30  val dretEvent  = Module(new DretEventModule)
31
32  val events: Seq[Module with CSREventBase] = Seq(
33    trapEntryDEvent,
34    trapEntryMEvent,
35    trapEntryHSEvent,
36    trapEntryVSEvent,
37    mretEvent,
38    sretEvent,
39    dretEvent,
40  )
41
42  events.foreach(x => dontTouch(x.out))
43
44  val trapEntryEvents: Seq[Module with CSREventBase] = Seq(
45    trapEntryDEvent,
46    trapEntryMEvent,
47    trapEntryHSEvent,
48    trapEntryVSEvent,
49  )
50}
51
52trait EventUpdatePrivStateOutput {
53  val privState = ValidIO(new PrivState)
54}
55
56trait EventOutputBase {
57  def getBundleByName(name: String): Valid[CSRBundle]
58}
59
60trait CSREventBase {
61  val valid = IO(Input(Bool()))
62  val in: Bundle
63  val out: Bundle
64
65  def genTrapVA(
66    transMode: PrivState,
67    satp: SatpBundle,
68    vsatp: SatpBundle,
69    hgatp: HgatpBundle,
70    addr: UInt,
71  ) = {
72    require(addr.getWidth >= 50)
73
74    val isBare =
75      transMode.isModeM ||
76      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Bare ||
77      transMode.isVirtual    && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare
78    val isSv39 =
79      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Sv39 ||
80      transMode.isVirtual    && vsatp.MODE === SatpMode.Sv39
81    val isSv48 =
82      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Sv48 ||
83      transMode.isVirtual    && vsatp.MODE === SatpMode.Sv48
84    val isSv39x4 =
85      transMode.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4
86    val isSv48x4 =
87      transMode.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4
88
89    val bareAddr   = ZeroExt(addr(PAddrWidth - 1, 0), XLEN)
90    // When enable virtual memory, the higher bit should fill with the msb of address of Sv39/Sv48/Sv57
91    val sv39Addr   = SignExt(addr.take(39), XLEN)
92    val sv39x4Addr = ZeroExt(addr.take(39 + 2), XLEN)
93    val sv48Addr   = SignExt(addr.take(48), XLEN)
94    val sv48x4Addr = ZeroExt(addr.take(48 + 2), XLEN)
95
96    val trapAddr = Mux1H(Seq(
97      isBare   -> bareAddr,
98      isSv39   -> sv39Addr,
99      isSv39x4 -> sv39x4Addr,
100      isSv48   -> sv48Addr,
101      isSv48x4 -> sv48x4Addr,
102    ))
103
104    trapAddr
105  }
106}
107
108class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSParameter {
109  val causeNO = Input(new CauseBundle)
110  val trapPc = Input(UInt(VaddrMaxWidth.W))
111  val trapPcGPA = Input(UInt(GPAddrBits.W))
112  val trapInst = Input(ValidIO(UInt(InstWidth.W)))
113  val isCrossPageIPF = Input(Bool())
114  val isHls = Input(Bool())
115
116  // always current privilege
117  val iMode = Input(new PrivState())
118  // take MRPV into consideration
119  val dMode = Input(new PrivState())
120  // status
121  val privState = Input(new PrivState)
122  val mstatus = Input(new MstatusBundle)
123  val hstatus = Input(new HstatusBundle)
124  val sstatus = Input(new SstatusBundle)
125  val vsstatus = Input(new SstatusBundle)
126
127  val tcontrol = Input(new TcontrolBundle)
128
129  val pcFromXtvec = Input(UInt(VaddrMaxWidth.W))
130
131  val satp = Input(new SatpBundle)
132  val vsatp = Input(new SatpBundle)
133  val hgatp = Input(new HgatpBundle)
134  // from mem
135  val memExceptionVAddr = Input(UInt(VAddrBits.W))
136  val memExceptionGPAddr = Input(UInt(GPAddrBits.W))
137}
138