xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala (revision a1cad1a90fb20e2bc4c3aed17666c71cc0d5466f) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.{ExceptionNO, HasXSParameter}
8import xiangshan.ExceptionNO._
9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState}
10import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState}
11import xiangshan.backend.fu.NewCSR.CSRConfig._
12import xiangshan.backend.fu.NewCSR._
13
14trait CSREvents { self: NewCSR =>
15  val trapEntryMEvent = Module(new TrapEntryMEventModule)
16
17  val trapEntryHSEvent = Module(new TrapEntryHSEventModule)
18
19  val trapEntryVSEvent = Module(new TrapEntryVSEventModule)
20
21  val mretEvent = Module(new MretEventModule)
22
23  val sretEvent = Module(new SretEventModule)
24
25  val dretEvent = Module(new DretEventModule)
26
27  val wfiEvent  = Module(new WfiEventModule)
28
29  val events: Seq[Module with CSREventBase] = Seq(
30    trapEntryMEvent,
31    trapEntryHSEvent,
32    trapEntryVSEvent,
33    mretEvent,
34    sretEvent,
35    dretEvent,
36    wfiEvent,
37  )
38
39  events.foreach(x => dontTouch(x.out))
40
41  val trapEntryEvents: Seq[Module with CSREventBase] = Seq(
42    trapEntryMEvent,
43    trapEntryHSEvent,
44    trapEntryVSEvent,
45  )
46}
47
48trait EventUpdatePrivStateOutput {
49  val privState = ValidIO(new PrivState)
50}
51
52trait EventOutputBase {
53  def getBundleByName(name: String): Valid[CSRBundle]
54}
55
56trait CSREventBase {
57  val valid = IO(Input(Bool()))
58  val in: Bundle
59  val out: Bundle
60}
61
62class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSParameter {
63  val causeNO = Input(new CauseBundle)
64  val trapPc = Input(UInt(VaddrMaxWidth.W))
65  val isCrossPageIPF = Input(Bool())
66
67  // always current privilege
68  val iMode = Input(new PrivState())
69  // take MRPV into consideration
70  val dMode = Input(new PrivState())
71  // status
72  val privState = Input(new PrivState)
73  val mstatus = Input(new MstatusBundle)
74  val hstatus = Input(new HstatusBundle)
75  val sstatus = Input(new SstatusBundle)
76  val vsstatus = Input(new SstatusBundle)
77
78  val pcFromXtvec = Input(UInt(VaddrMaxWidth.W))
79
80  val satp = Input(new SatpBundle)
81  val vsatp = Input(new SatpBundle)
82  // from mem
83  val memExceptionVAddr = Input(UInt(VAddrBits.W))
84  val memExceptionGPAddr = Input(UInt(GPAddrBits.W))
85}
86