xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala (revision 887862dbb8debde8ab099befc426493834a69ee7) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.HasXSParameter
8import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState}
9import xiangshan.backend.fu.NewCSR.CSRConfig._
10import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, SatpMode}
11import xiangshan.backend.fu.NewCSR._
12
13trait CSREvents { self: NewCSR =>
14  val trapEntryDEvent = Module(new TrapEntryDEventModule)
15
16  val trapEntryMEvent = Module(new TrapEntryMEventModule)
17
18  val trapEntryHSEvent = Module(new TrapEntryHSEventModule)
19
20  val trapEntryVSEvent = Module(new TrapEntryVSEventModule)
21
22  val mretEvent = Module(new MretEventModule)
23
24  val sretEvent = Module(new SretEventModule)
25
26  val dretEvent = Module(new DretEventModule)
27
28  val events: Seq[Module with CSREventBase] = Seq(
29    trapEntryDEvent,
30    trapEntryMEvent,
31    trapEntryHSEvent,
32    trapEntryVSEvent,
33    mretEvent,
34    sretEvent,
35    dretEvent,
36  )
37
38  events.foreach(x => dontTouch(x.out))
39
40  val trapEntryEvents: Seq[Module with CSREventBase] = Seq(
41    trapEntryDEvent,
42    trapEntryMEvent,
43    trapEntryHSEvent,
44    trapEntryVSEvent,
45  )
46}
47
48trait EventUpdatePrivStateOutput {
49  val privState = ValidIO(new PrivState)
50}
51
52trait EventOutputBase {
53  def getBundleByName(name: String): Valid[CSRBundle]
54}
55
56trait CSREventBase {
57  val valid = IO(Input(Bool()))
58  val in: Bundle
59  val out: Bundle
60
61  def genTrapVA(
62    transMode: PrivState,
63    satp: SatpBundle,
64    vsatp: SatpBundle,
65    hgatp: HgatpBundle,
66    addr: UInt,
67  ) = {
68    require(addr.getWidth >= 50)
69
70    val isBare =
71      transMode.isModeM ||
72      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Bare ||
73      transMode.isVirtual    && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare
74    val isSv39 =
75      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Sv39 ||
76      transMode.isVirtual    && vsatp.MODE === SatpMode.Sv39
77    val isSv48 =
78      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Sv48 ||
79      transMode.isVirtual    && vsatp.MODE === SatpMode.Sv48
80    val isSv39x4 =
81      transMode.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4
82    val isSv48x4 =
83      transMode.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4
84
85    val bareAddr   = ZeroExt(addr(PAddrWidth - 1, 0), XLEN)
86    // When enable virtual memory, the higher bit should fill with the msb of address of Sv39/Sv48/Sv57
87    val sv39Addr   = SignExt(addr.take(39), XLEN)
88    val sv39x4Addr = ZeroExt(addr.take(39 + 2), XLEN)
89    val sv48Addr   = SignExt(addr.take(48), XLEN)
90    val sv48x4Addr = ZeroExt(addr.take(48 + 2), XLEN)
91
92    val trapAddr = Mux1H(Seq(
93      isBare   -> bareAddr,
94      isSv39   -> sv39Addr,
95      isSv39x4 -> sv39x4Addr,
96      isSv48   -> sv48Addr,
97      isSv48x4 -> sv48x4Addr,
98    ))
99
100    trapAddr
101  }
102}
103
104class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSParameter {
105  val causeNO = Input(new CauseBundle)
106  val trapPc = Input(UInt(VaddrMaxWidth.W))
107  val trapPcGPA = Input(UInt(GPAddrBits.W))
108  val trapInst = Input(ValidIO(UInt(InstWidth.W)))
109  val isCrossPageIPF = Input(Bool())
110  val isHls = Input(Bool())
111
112  // always current privilege
113  val iMode = Input(new PrivState())
114  // take MRPV into consideration
115  val dMode = Input(new PrivState())
116  // status
117  val privState = Input(new PrivState)
118  val mstatus = Input(new MstatusBundle)
119  val hstatus = Input(new HstatusBundle)
120  val sstatus = Input(new SstatusBundle)
121  val vsstatus = Input(new SstatusBundle)
122
123  val tcontrol = Input(new TcontrolBundle)
124
125  val pcFromXtvec = Input(UInt(VaddrMaxWidth.W))
126
127  val satp = Input(new SatpBundle)
128  val vsatp = Input(new SatpBundle)
129  val hgatp = Input(new HgatpBundle)
130  // from mem
131  val memExceptionVAddr = Input(UInt(VAddrBits.W))
132  val memExceptionGPAddr = Input(UInt(GPAddrBits.W))
133}
134