xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala (revision 260a087d23a27f413c006362a82c84ecef09a587) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.HasXSParameter
8import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState}
9import xiangshan.backend.fu.NewCSR.CSRConfig._
10import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, SatpMode}
11import xiangshan.backend.fu.NewCSR._
12
13trait CSREvents { self: NewCSR =>
14  val trapEntryMEvent = Module(new TrapEntryMEventModule)
15
16  val trapEntryHSEvent = Module(new TrapEntryHSEventModule)
17
18  val trapEntryVSEvent = Module(new TrapEntryVSEventModule)
19
20  val mretEvent = Module(new MretEventModule)
21
22  val sretEvent = Module(new SretEventModule)
23
24  val dretEvent = Module(new DretEventModule)
25
26  val events: Seq[Module with CSREventBase] = Seq(
27    trapEntryMEvent,
28    trapEntryHSEvent,
29    trapEntryVSEvent,
30    mretEvent,
31    sretEvent,
32    dretEvent,
33  )
34
35  events.foreach(x => dontTouch(x.out))
36
37  val trapEntryEvents: Seq[Module with CSREventBase] = Seq(
38    trapEntryMEvent,
39    trapEntryHSEvent,
40    trapEntryVSEvent,
41  )
42}
43
44trait EventUpdatePrivStateOutput {
45  val privState = ValidIO(new PrivState)
46}
47
48trait EventOutputBase {
49  def getBundleByName(name: String): Valid[CSRBundle]
50}
51
52trait CSREventBase {
53  val valid = IO(Input(Bool()))
54  val in: Bundle
55  val out: Bundle
56
57  def genTrapVA(
58    transMode: PrivState,
59    satp: SatpBundle,
60    vsatp: SatpBundle,
61    hgatp: HgatpBundle,
62    addr: UInt,
63  ) = {
64    require(addr.getWidth >= 41)
65
66    val isBare =
67      transMode.isModeM ||
68      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Bare ||
69      transMode.isVirtual    && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare
70    val isSv39 =
71      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Sv39 ||
72      transMode.isVirtual    && vsatp.MODE === SatpMode.Sv39
73    val isSv48 =
74      transMode.isModeHSorHU &&  satp.MODE === SatpMode.Sv48 ||
75      transMode.isVirtual    && vsatp.MODE === SatpMode.Sv48
76    val isSv39x4 =
77      transMode.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4
78    val isSv48x4 =
79      transMode.isVirtual && vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4
80
81    val bareAddr   = ZeroExt(addr(PAddrWidth - 1, 0), XLEN)
82    // When enable virtual memory, the higher bit should fill with the msb of address of Sv39/Sv48/Sv57
83    val sv39Addr   = SignExt(addr(38, 0), XLEN)
84    val sv39x4Addr = SignExt(addr(40, 0), XLEN)
85
86    val trapAddr = Mux1H(Seq(
87      isBare -> bareAddr,
88      isSv39 -> sv39Addr,
89      isSv39x4 -> sv39x4Addr,
90    ))
91
92    trapAddr
93  }
94}
95
96class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSParameter {
97  val causeNO = Input(new CauseBundle)
98  val trapPc = Input(UInt(VaddrMaxWidth.W))
99  val isCrossPageIPF = Input(Bool())
100
101  // always current privilege
102  val iMode = Input(new PrivState())
103  // take MRPV into consideration
104  val dMode = Input(new PrivState())
105  // status
106  val privState = Input(new PrivState)
107  val mstatus = Input(new MstatusBundle)
108  val hstatus = Input(new HstatusBundle)
109  val sstatus = Input(new SstatusBundle)
110  val vsstatus = Input(new SstatusBundle)
111
112  val pcFromXtvec = Input(UInt(VaddrMaxWidth.W))
113
114  val satp = Input(new SatpBundle)
115  val vsatp = Input(new SatpBundle)
116  val hgatp = Input(new HgatpBundle)
117  // from mem
118  val memExceptionVAddr = Input(UInt(VAddrBits.W))
119  val memExceptionGPAddr = Input(UInt(GPAddrBits.W))
120}
121