xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala (revision 1e7040bae63b5722e6e61f07844e884631389c33) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.{ExceptionNO, HasXSParameter}
8import xiangshan.ExceptionNO._
9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState}
10import xiangshan.backend.fu.NewCSR.CSRConfig._
11import xiangshan.backend.fu.NewCSR.CSRDefines._
12import xiangshan.backend.fu.NewCSR._
13import xiangshan.backend.fu.util.CSRConst
14
15trait CSREvents { self: NewCSR =>
16  val trapEntryMEvent = Module(new TrapEntryMEventModule)
17
18  val trapEntryHSEvent = Module(new TrapEntryHSEventModule)
19
20  val trapEntryVSEvent = Module(new TrapEntryVSEventModule)
21
22  val mretEvent = Module(new MretEventModule)
23
24  val sretEvent = Module(new SretEventModule)
25
26  val dretEvent = Module(new DretEventModule)
27
28  val events: Seq[Module with CSREventBase] = Seq(
29    trapEntryMEvent,
30    trapEntryHSEvent,
31    trapEntryVSEvent,
32    mretEvent,
33    sretEvent,
34    dretEvent,
35  )
36
37  events.foreach(x => dontTouch(x.out))
38
39  val trapEntryEvents: Seq[Module with CSREventBase] = Seq(
40    trapEntryMEvent,
41    trapEntryHSEvent,
42    trapEntryVSEvent,
43  )
44}
45
46trait EventUpdatePrivStateOutput {
47  val privState = ValidIO(new PrivState)
48}
49
50trait EventOutputBase {
51  def getBundleByName(name: String): Valid[CSRBundle]
52}
53
54trait CSREventBase {
55  val valid = IO(Input(Bool()))
56  val in: Bundle
57  val out: Bundle
58}
59
60class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSParameter {
61  val causeNO = Input(new CauseBundle)
62  val trapPc = Input(UInt(VaddrMaxWidth.W))
63  val isCrossPageIPF = Input(Bool())
64
65  // always current privilege
66  val iMode = Input(new PrivState())
67  // take MRPV into consideration
68  val dMode = Input(new PrivState())
69  // status
70  val privState = Input(new PrivState)
71  val mstatus = Input(new MstatusBundle)
72  val hstatus = Input(new HstatusBundle)
73  val sstatus = Input(new SstatusBundle)
74  val vsstatus = Input(new SstatusBundle)
75  val satp = Input(new SatpBundle)
76  val vsatp = Input(new SatpBundle)
77  // from mem
78  val memExceptionVAddr = Input(UInt(VAddrBits.W))
79  val memExceptionGPAddr = Input(UInt(GPAddrBits.W))
80}
81