xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala (revision 0c2ba7ae92b161da91211da8693156dfc642570f) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.{ExceptionNO, HasXSParameter}
8import xiangshan.ExceptionNO._
9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState}
10import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState}
11import xiangshan.backend.fu.NewCSR.CSRConfig._
12import xiangshan.backend.fu.NewCSR._
13
14trait CSREvents { self: NewCSR =>
15  val trapEntryMEvent = Module(new TrapEntryMEventModule)
16
17  val trapEntryHSEvent = Module(new TrapEntryHSEventModule)
18
19  val trapEntryVSEvent = Module(new TrapEntryVSEventModule)
20
21  val mretEvent = Module(new MretEventModule)
22
23  val sretEvent = Module(new SretEventModule)
24
25  val dretEvent = Module(new DretEventModule)
26
27  val events: Seq[Module with CSREventBase] = Seq(
28    trapEntryMEvent,
29    trapEntryHSEvent,
30    trapEntryVSEvent,
31    mretEvent,
32    sretEvent,
33    dretEvent,
34  )
35
36  events.foreach(x => dontTouch(x.out))
37
38  val trapEntryEvents: Seq[Module with CSREventBase] = Seq(
39    trapEntryMEvent,
40    trapEntryHSEvent,
41    trapEntryVSEvent,
42  )
43}
44
45trait EventUpdatePrivStateOutput {
46  val privState = ValidIO(new PrivState)
47}
48
49trait EventOutputBase {
50  def getBundleByName(name: String): Valid[CSRBundle]
51}
52
53trait CSREventBase {
54  val valid = IO(Input(Bool()))
55  val in: Bundle
56  val out: Bundle
57}
58
59class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSParameter {
60  val causeNO = Input(new CauseBundle)
61  val trapPc = Input(UInt(VaddrMaxWidth.W))
62  val isCrossPageIPF = Input(Bool())
63
64  // always current privilege
65  val iMode = Input(new PrivState())
66  // take MRPV into consideration
67  val dMode = Input(new PrivState())
68  // status
69  val privState = Input(new PrivState)
70  val mstatus = Input(new MstatusBundle)
71  val hstatus = Input(new HstatusBundle)
72  val sstatus = Input(new SstatusBundle)
73  val vsstatus = Input(new SstatusBundle)
74
75  val pcFromXtvec = Input(UInt(VaddrMaxWidth.W))
76
77  val satp = Input(new SatpBundle)
78  val vsatp = Input(new SatpBundle)
79  // from mem
80  val memExceptionVAddr = Input(UInt(VAddrBits.W))
81  val memExceptionGPAddr = Input(UInt(GPAddrBits.W))
82}
83