xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala (revision b03c55a5df5dc8793cb44b42dd60141566e57e78) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import freechips.rocketchip.util._
6import org.chipsalliance.cde.config.Parameters
7import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRRWField => RW}
8import xiangshan.HasXSParameter
9
10import scala.collection.immutable.SeqMap
11
12trait CSRCustom { self: NewCSR =>
13  // Supervisor Custom Read/Write
14  val sbpctl = Module(new CSRModule("Sbpctl", new SbpctlBundle))
15    .setAddr(0x5C0)
16
17  val spfctl = Module(new CSRModule("Spfctl", new SpfctlBundle))
18    .setAddr(0x5C1)
19
20  // slvpredctl: load violation predict settings
21  // Default reset period: 2^16
22  // why this number: reset more frequently while keeping the overhead low
23  // Overhead: extra two redirections in every 64K cycles => ~0.1% overhead
24  val slvpredctl = Module(new CSRModule("Slvpredctl", new SlvpredctlBundle))
25    .setAddr(0x5C2)
26
27  // smblockctl: memory block configurations
28  val smblockctl = Module(new CSRModule("Smblockctl", new SmblockctlBundle))
29    .setAddr(0x5C3)
30
31  val srnctl = Module(new CSRModule("Srnctl", new SrnctlBundle))
32    .setAddr(0x5C4)
33
34  val sfetchctl = Module(new CSRModule("Sfetchctl", new SfetchctlBundle))
35    .setAddr(0x9E0)
36
37  val customCSRMods = Seq(
38    sbpctl,
39    spfctl,
40    slvpredctl,
41    smblockctl,
42    srnctl,
43    sfetchctl,
44  )
45
46  val customCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_ <: CSRBundle], UInt)] = SeqMap.from(
47    customCSRMods.map(csr => (csr.addr -> (csr.w -> csr.rdata))).iterator
48  )
49
50  val customCSROutMap: SeqMap[Int, UInt] = SeqMap.from(
51    customCSRMods.map(csr => (csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt)).iterator
52  )
53}
54
55class SbpctlBundle extends CSRBundle {
56  val LOOP_ENABLE = RW(6).withReset(true.B)
57  val RAS_ENABLE  = RW(5).withReset(true.B)
58  val SC_ENABLE   = RW(4).withReset(true.B)
59  val TAGE_ENABLE = RW(3).withReset(true.B)
60  val BIM_ENABLE  = RW(2).withReset(true.B)
61  val BTB_ENABLE  = RW(1).withReset(true.B)
62  val UBTB_ENABLE = RW(0).withReset(true.B)
63}
64
65class SpfctlBundle extends CSRBundle {
66  // turn off L2 BOP, turn on L1 SMS by default
67  val L2_PF_STORE_ONLY        = RW(    17).withReset(false.B)     // L2 pf store only
68  val L1D_PF_ENABLE_STRIDE    = RW(    16).withReset(true.B)      // L1D prefetch enable stride
69  val L1D_PF_ACTIVE_STRIDE    = SpfctlL1DPfActiveStride(15, 10).withReset(SpfctlL1DPfActiveStride.initValue)   // L1D prefetch active page stride
70  val L1D_PF_ACTIVE_THRESHOLD = SpfctlL1DPfActiveThreshold( 9,  6).withReset(SpfctlL1DPfActiveThreshold.initValue)   // L1D prefetch active page threshold
71  val L1D_PF_ENABLE_PHT       = RW(     5).withReset(true.B)      // L1D prefetch enable pht
72  val L1D_PF_ENABLE_AGT       = RW(     4).withReset(true.B)      // L1D prefetch enable agt
73  val L1D_PF_TRAIN_ON_HIT     = RW(     3).withReset(false.B)     // L1D train prefetch on hit
74  val L1D_PF_ENABLE           = RW(     2).withReset(true.B)      // L1D Cache Prefetcher Enable
75  val L2_PF_ENABLE            = RW(     1).withReset(true.B)      // L2  Cache Prefetcher Enable
76  val L1I_PF_ENABLE           = RW(     0).withReset(true.B)      // L1I Cache Prefetcher Enable
77}
78
79class SlvpredctlBundle extends CSRBundle {
80  val LVPRED_TIMEOUT          = SlvpredCtlTimeOut(8, 4).withReset(SlvpredCtlTimeOut.initValue)
81  val STORESET_NO_FAST_WAKEUP = RW(3).withReset(false.B)
82  val STORESET_WAIT_STORE     = RW(2).withReset(false.B)
83  val NO_SPEC_LOAD            = RW(1).withReset(false.B)
84  val LVPRED_DISABLE          = RW(0).withReset(false.B)
85}
86
87class SmblockctlBundle extends CSRBundle {
88  val UNCACHE_WRITE_OUTSTANDING_ENABLE = RW(   7).withReset(false.B)  // Enable uncache write outstanding (0).
89  val CACHE_ERROR_ENABLE               = RW(   6).withReset(true.B)   // Enable cache error after reset (CE).
90  val SOFT_PREFETCH_ENABLE             = RW(   5).withReset(true.B)   // Enable soft-prefetch after reset (SP).
91  val LDLD_VIO_CHECK_ENABLE            = RW(   4).withReset(true.B)   // Enable load load violation check after reset (LVC).
92  val SBUFFER_THRESHOLD                = SbufferThreshold(3, 0).withReset(SbufferThreshold.initValue) // Store buffer flush threshold (Th).
93}
94
95class SrnctlBundle extends CSRBundle {
96  val WFI_ENABLE     = RW(2).withReset(true.B)
97  val FUSION_ENABLE  = RW(0).withReset(true.B)
98}
99
100class SfetchctlBundle extends CSRBundle {
101  val ICACHE_PARITY_ENABLE = RW(0).withReset(false.B) // L1I Cache Parity check enable
102}
103
104object SbufferThreshold extends CSREnum with RWApply {
105  val initValue = Value(7.U)
106}
107
108object SpfctlL1DPfActiveStride extends CSREnum with RWApply {
109  val initValue = Value(30.U)
110}
111
112object SpfctlL1DPfActiveThreshold extends CSREnum with RWApply {
113  val initValue = Value(12.U)
114}
115
116object SlvpredCtlTimeOut extends CSREnum with RWApply {
117  val initValue = Value(3.U)
118}
119
120