1package xiangshan.backend.fu.NewCSR 2 3import chisel3._ 4import chisel3.util._ 5import freechips.rocketchip.util._ 6import org.chipsalliance.cde.config.Parameters 7import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRRWField => RW} 8import xiangshan.HasXSParameter 9 10import scala.collection.immutable.SeqMap 11 12trait CSRCustom { self: NewCSR => 13 // Supervisor Custom Read/Write 14 val sbpctl = Module(new CSRModule("Sbpctl", new SbpctlBundle)) 15 .setAddr(0x5C0) 16 17 val spfctl = Module(new CSRModule("Spfctl", new SpfctlBundle)) 18 .setAddr(0x5C1) 19 20 // slvpredctl: load violation predict settings 21 // Default reset period: 2^16 22 // why this number: reset more frequently while keeping the overhead low 23 // Overhead: extra two redirections in every 64K cycles => ~0.1% overhead 24 val slvpredctl = Module(new CSRModule("Slvpredctl", new SlvpredctlBundle)) 25 .setAddr(0x5C2) 26 27 // smblockctl: memory block configurations 28 val smblockctl = Module(new CSRModule("Smblockctl", new SmblockctlBundle)) 29 .setAddr(0x5C3) 30 31 val srnctl = Module(new CSRModule("Srnctl", new SrnctlBundle)) 32 .setAddr(0x5C4) 33 34 val customCSRMods = Seq( 35 sbpctl, 36 spfctl, 37 slvpredctl, 38 smblockctl, 39 srnctl, 40 ) 41 42 val customCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_ <: CSRBundle], UInt)] = SeqMap.from( 43 customCSRMods.map(csr => (csr.addr -> (csr.w -> csr.rdata))).iterator 44 ) 45 46 val customCSROutMap: SeqMap[Int, UInt] = SeqMap.from( 47 customCSRMods.map(csr => (csr.addr -> csr.regOut.asInstanceOf[CSRBundle].asUInt)).iterator 48 ) 49} 50 51class SbpctlBundle extends CSRBundle { 52 val LOOP_ENABLE = RW(6).withReset(true.B) 53 val RAS_ENABLE = RW(5).withReset(true.B) 54 val SC_ENABLE = RW(4).withReset(true.B) 55 val TAGE_ENABLE = RW(3).withReset(true.B) 56 val BIM_ENABLE = RW(2).withReset(true.B) 57 val BTB_ENABLE = RW(1).withReset(true.B) 58 val UBTB_ENABLE = RW(0).withReset(true.B) 59} 60 61class SpfctlBundle extends CSRBundle { 62 // turn off L2 BOP, turn on L1 SMS by default 63 val L2_PF_STORE_ONLY = RW( 17).withReset(false.B) // L2 pf store only 64 val L1D_PF_ENABLE_STRIDE = RW( 16).withReset(true.B) // L1D prefetch enable stride 65 val L1D_PF_ACTIVE_STRIDE = SpfctlL1DPfActiveStride(15, 10).withReset(SpfctlL1DPfActiveStride.initValue) // L1D prefetch active page stride 66 val L1D_PF_ACTIVE_THRESHOLD = SpfctlL1DPfActiveThreshold( 9, 6).withReset(SpfctlL1DPfActiveThreshold.initValue) // L1D prefetch active page threshold 67 val L1D_PF_ENABLE_PHT = RW( 5).withReset(true.B) // L1D prefetch enable pht 68 val L1D_PF_ENABLE_AGT = RW( 4).withReset(true.B) // L1D prefetch enable agt 69 val L1D_PF_TRAIN_ON_HIT = RW( 3).withReset(false.B) // L1D train prefetch on hit 70 val L1D_PF_ENABLE = RW( 2).withReset(true.B) // L1D Cache Prefetcher Enable 71 val L2_PF_ENABLE = RW( 1).withReset(true.B) // L2 Cache Prefetcher Enable 72 val L1I_PF_ENABLE = RW( 0).withReset(true.B) // L1I Cache Prefetcher Enable 73} 74 75class SlvpredctlBundle extends CSRBundle { 76 val LVPRED_TIMEOUT = SlvpredCtlTimeOut(8, 4).withReset(SlvpredCtlTimeOut.initValue) 77 val STORESET_NO_FAST_WAKEUP = RW(3).withReset(false.B) 78 val STORESET_WAIT_STORE = RW(2).withReset(false.B) 79 val NO_SPEC_LOAD = RW(1).withReset(false.B) 80 val LVPRED_DISABLE = RW(0).withReset(false.B) 81} 82 83class SmblockctlBundle extends CSRBundle { 84 val HD_MISALIGN_LD_ENABLE = RW( 9).withReset(true.B) // Enable hardware load misalign. 85 val HD_MISALIGN_ST_ENABLE = RW( 8).withReset(true.B) // Enable hardware store misalign. 86 val UNCACHE_WRITE_OUTSTANDING_ENABLE = RW( 7).withReset(false.B) // Enable uncache write outstanding (0). 87 val CACHE_ERROR_ENABLE = RW( 6).withReset(true.B) // Enable cache error after reset (CE). 88 val SOFT_PREFETCH_ENABLE = RW( 5).withReset(true.B) // Enable soft-prefetch after reset (SP). 89 val LDLD_VIO_CHECK_ENABLE = RW( 4).withReset(true.B) // Enable load load violation check after reset (LVC). 90 val SBUFFER_THRESHOLD = SbufferThreshold(3, 0).withReset(SbufferThreshold.initValue) // Store buffer flush threshold (Th). 91} 92 93class SrnctlBundle extends CSRBundle { 94 val WFI_ENABLE = RW(2).withReset(true.B) 95 val FUSION_ENABLE = RW(0).withReset(true.B) 96} 97 98object SbufferThreshold extends CSREnum with RWApply { 99 val initValue = Value(7.U) 100} 101 102object SpfctlL1DPfActiveStride extends CSREnum with RWApply { 103 val initValue = Value(30.U) 104} 105 106object SpfctlL1DPfActiveThreshold extends CSREnum with RWApply { 107 val initValue = Value(12.U) 108} 109 110object SlvpredCtlTimeOut extends CSREnum with RWApply { 111 val initValue = Value(3.U) 112} 113 114